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This is a general list of ports and registers used to control features of the Spectrum Next.


This is a general list of ports and registers used to control features on the Spectrum Next board.
== About The Content of this Page ==


Note that these lists are automatically generated and not directly editable. To edit data on a port or register, visit its page. To add a new port, click [[Form:Port Form|here]]. To add a new register, click [[Form:Next Configuration Register Form|here]].
This page features the list of the Next ports and control registers.


= Mapped Spectrum Ports =  
A partial replacement to some of the content that the old codebase provided has been migrated to https://explorer.specnext.dev/ - this site is still under active development, but aims to be an automated way to explore the contents of official specification & documents.
 
{| class="wikitable"
! The information is manually copied from the specification, so if something is off or missing, check the gitlab repository of ZX Next FPGA core: [https://gitlab.com/SpectrumNext/ZX_Spectrum_Next_FPGA/-/blob/master/cores/zxnext/ports.txt ports.txt] and [https://gitlab.com/SpectrumNext/ZX_Spectrum_Next_FPGA/-/blob/master/cores/zxnext/nextreg.txt nextreg.txt] and [https://gitlab.com/SpectrumNext/ZX_Spectrum_Next_FPGA/-/blob/master/cores/zxnext/changelog.md changelog.md].
|}
 
= Mapped Next Ports =  


===A note on partial decoding===
===A note on partial decoding===
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On the other hand, partial decoding can allow use of the multiple output opcodes such as OTIR, which normally places the loop counter on the top half of the address bus - thus making it useless except for devices which ignore this top half. This is the reason why some of the Next registers do ignore the top half of the port address.
On the other hand, partial decoding can allow use of the multiple output opcodes such as OTIR, which normally places the loop counter on the top half of the address bus - thus making it useless except for devices which ignore this top half. This is the reason why some of the Next registers do ignore the top half of the port address.
 
{{#ask:
=== The list of ports ===
[[Category:Port]]
 
|?PortNumber=Hexadecimal
The following ports are currently documented in this wiki:
|?NumberDec#-=Decimal
* {{PortNo|$xxFE}} [[ULA Control Port]] and [[Keyboard]]
|?PortMask=Mask
* {{PortNo|$103B}} [[I2C clock]]
|?ShortDesc=Description
* {{PortNo|$113B}} [[I2C data]]
|sort=PortNumber
* {{PortNo|$123B}} [[Layer 2 Access Port]]
}}
* {{PortNo|$133B}} [[UART TX]]
* {{PortNo|$143B}} [[UART RX]]
* {{PortNo|$153B}} [[UART Control]]
* {{PortNo|$163B}} [[UART Frame]]
* {{PortNo|$183B}} [[CTC Channels]]
* {{PortNo|$1FFD}} [[Plus 3 Memory Paging Control]]
* {{PortNo|$243B}} [[TBBlue Register Select]]
* {{PortNo|$253B}} [[TBBlue Register Access]]
* {{PortNo|$303B}} [[Sprite Status/Slot Select]]
* {{PortNo|$7FFD}} [[Memory Paging Control]]
* {{PortNo|$BFF5}} [[AY Info]]
* {{PortNo|$BFFD}} [[Sound Chip Register Write]]
* {{PortNo|$DFFD}} [[Next Memory Bank Select]]
* {{PortNo|$E3}} [[DIVMMC]]
* {{PortNo|$EFF7}} [[Pentagon 1024 paging]]
* {{PortNo|$FADF}} [[Kempston Mouse Buttons]]
* {{PortNo|$FBDF}} [[Kempston Mouse X]]
* {{PortNo|$FFDF}} [[Kempston Mouse Y]]
* {{PortNo|$FFFD}} [[Turbo Sound Next Control]]
* {{PortNo|$xx0B}} [[MB02 DMA Port]]
* {{PortNo|$xx1F}} [[Kempston Joystick]]
* {{PortNo|$xx37}} [[Kempston Joystick 2, Joystick I/O]]
* {{PortNo|$xx57}} [[Sprite Attribute Upload]]
* {{PortNo|$xx5B}} [[Sprite Pattern Upload]]
* {{PortNo|$xx6B}} [[Datagear DMA Port]]
* {{PortNo|$xxDF}} [[SpecDrum DAC Output]]
* {{PortNo|$xxFE}} [[ULA Control Port]]
* {{PortNo|$xxFF}} [[Timex Sinclair Video Mode Control]]


= Next/TBBlue Feature Control Registers =
= Next/TBBlue Feature Control Registers =
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Specific features of the Next are controlled via these register numbers, accessed via {{PortNo|$243B}} and {{PortNo|$253B}}, or via the NEXTREG [[Extended Z80 instruction set|opcode]].
Specific features of the Next are controlled via these register numbers, accessed via {{PortNo|$243B}} and {{PortNo|$253B}}, or via the NEXTREG [[Extended Z80 instruction set|opcode]].


{{#ask:
The following Next Registers are currently described in this wiki:
[[Category:Next Configuration Registers]]
 
|?TBRegisterNumber=Number |?TBRegisterReadable#Yes,No=Readable |?TBRegisterWritable#Yes,No=Writable |?ShortDesc=Description |limit=150 |sort=TBRegisterNumber
* [[NextReg:$00]] [[Machine ID Register]]
}}
* [[NextReg:$01]] [[Core Version Register]]
* [[NextReg:$02]] [[Reset Register]]
* [[NextReg:$03]] [[Machine Type Register]]
* [[NextReg:$04]] [[Config Mapping Register]]
* [[NextReg:$05]] [[Peripheral 1 Setting Register]]
* [[NextReg:$06]] [[Peripheral 2 Setting Register]]
* [[NextReg:$07]] [[CPU Speed Register]]
* [[NextReg:$08]] [[Peripheral 3 Setting Register]]
* [[NextReg:$09]] [[Peripheral 4 Setting Register]]
* [[NextReg:$0A]] [[Peripheral 5 Setting Register]]
* [[NextReg:$0B]] [[Joystick I/O Mode Register]]
* [[NextReg:$0E]] [[Core Version Register (sub minor)]]
* [[NextReg:$0F]] [[Board ID Register]]
* [[NextReg:$10]] [[Anti-brick Register]]
* [[NextReg:$11]] [[Video Timing Register]]
* [[NextReg:$12]] [[Layer 2 Active RAM Bank Register]]
* [[NextReg:$13]] [[Layer 2 Shadow RAM bank Register]]
* [[NextReg:$14]] [[Global Transparency Colour Register]]
* [[NextReg:$15]] [[Sprite and Layers System Register]]
* [[NextReg:$16]] [[Layer 2 X Scroll LSB Register]]
* [[NextReg:$17]] [[Layer 2 Y Scroll Register]]
* [[NextReg:$18]] [[Clip Window Layer 2 Register]]
* [[NextReg:$19]] [[Clip Window Sprites Register]]
* [[NextReg:$1A]] [[Clip Window ULA/LoRes Register]]
* [[NextReg:$1B]] [[Clip Window Tilemap Register]]
* [[NextReg:$1C]] [[Clip Window Control Register]]
* [[NextReg:$1E]] [[Active Video Line (MSB) Register]]
* [[NextReg:$1F]] [[Active Video Line (LSB) Register]]
* [[NextReg:$20]] [[Generate Maskable Interrupt Register]]
* [[NextReg:$22]] [[Video Line Interrupt Control Register]]
* [[NextReg:$23]] [[Video Line Interrupt Value Register]]
* [[NextReg:$24]] [[Reserved]]
* [[NextReg:$26]] [[ULA X Offset Register]]
* [[NextReg:$27]] [[ULA Y Offset Register]]
* [[NextReg:$28]] [[Keymap High Address Register]]
* [[NextReg:$29]] [[Keymap Low Address Register]]
* [[NextReg:$2A]] [[Keymap High Data Register]]
* [[NextReg:$2B]] [[Keymap Low Data Register]]
* [[NextReg:$2C]] [[DAC B Mirror (left) Register]]
* [[NextReg:$2D]] [[DAC A+D Mirror (mono) Register]]
* [[NextReg:$2E]] [[DAC C Mirror (right) Register]]
* [[NextReg:$2F]] [[Tilemap X Scroll MSB Register]]
* [[NextReg:$30]] [[Tilemap X Scroll LSB Register]]
* [[NextReg:$31]] [[Tilemap Offset Y Register]]
* [[NextReg:$32]] [[LoRes X Scroll Register]]
* [[NextReg:$33]] [[LoRes Y Scroll Register]]
* [[NextReg:$34]] [[Sprite port-mirror Index Register]]
* [[NextReg:$35]] [[Sprite Attribute 0 Register]]
* [[NextReg:$36]] [[Sprite Attribute 1 Register]]
* [[NextReg:$37]] [[Sprite Attribute 2 Register]]
* [[NextReg:$38]] [[Sprite Attribute 3 Register]]
* [[NextReg:$39]] [[Sprite Attribute 4 Register]]
* [[NextReg:$40]] [[Palette Index Register]]
* [[NextReg:$41]] [[Palette Value (8 bit colour) Register]]
* [[NextReg:$42]] [[ULANext Attribute Byte Format Register]]
* [[NextReg:$43]] [[ULA Palette Control Register]]
* [[NextReg:$44]] [[Palette Value (9 bit colour) Register]]
* [[NextReg:$4A]] [[Fallback Colour Register]]
* [[NextReg:$4B]] [[Sprite Transparency Index Register]]
* [[NextReg:$4C]] [[Tilemap Transparency Index Register]]
* [[NextReg:$50]] [[MMU slot 0 Register]]
* [[NextReg:$51]] [[MMU slot 1 Register]]
* [[NextReg:$52]] [[MMU slot 2 Register]]
* [[NextReg:$53]] [[MMU slot 3 Register]]
* [[NextReg:$54]] [[MMU slot 4 Register]]
* [[NextReg:$55]] [[MMU slot 5 Register]]
* [[NextReg:$56]] [[MMU slot 6 Register]]
* [[NextReg:$57]] [[MMU slot 7 Register]]
* [[NextReg:$60]] [[Copper Data 8-bit Write Register]]
* [[NextReg:$61]] [[Copper Address LSB Register]]
* [[NextReg:$62]] [[Copper Control Register]]
* [[NextReg:$63]] [[Copper Data 16-bit Write Register]]
* [[NextReg:$64]] [[Vertical Line Count Offset Register]]
* [[NextReg:$68]] [[ULA Control Register]]
* [[NextReg:$69]] [[Display Control 1 Register]]
* [[NextReg:$6A]] [[LoRes Control Register]]
* [[NextReg:$6B]] [[Tilemap Control Register]]
* [[NextReg:$6C]] [[Default Tilemap Attribute Register]]
* [[NextReg:$6E]] [[Tilemap Base Address Register]]
* [[NextReg:$6F]] [[Tile Definitions Base Address Register]]
* [[NextReg:$70]] [[Layer 2 Control Register]]
* [[NextReg:$71]] [[Layer 2 X Scroll MSB Register]]
* [[NextReg:$75]] [[Sprite Attribute 0 (with INC) Register]]
* [[NextReg:$76]] [[Sprite Attribute 1 (with INC) Register]]
* [[NextReg:$77]] [[Sprite Attribute 2 (with INC) Register]]
* [[NextReg:$78]] [[Sprite Attribute 3 (with INC) Register]]
* [[NextReg:$79]] [[Sprite Attribute 4 (with INC) Register]]
* [[NextReg:$7F]] [[User Storage 0 Register]]
* [[NextReg:$80]] [[Expansion Bus Enable Register]]
* [[NextReg:$81]] [[Expansion Bus Control Register]]
* [[NextReg:$82]] [[Internal Port Decoding b0-7 Register]]
* [[NextReg:$83]] [[Internal Port Decoding b8-15 Register]]
* [[NextReg:$84]] [[Internal Port Decoding b16-23 Register]]
* [[NextReg:$85]] [[Internal Port Decoding b24-31 Register]]
* [[NextReg:$86]] [[Expansion Bus Decoding b0-7 Register]]
* [[NextReg:$87]] [[Expansion Bus Decoding b8-15 Register]]
* [[NextReg:$88]] [[Expansion Bus Decoding b16-23 Register]]
* [[NextReg:$89]] [[Expansion Bus Decoding b24-31 Register]]
* [[NextReg:$8A]] [[Expansion Bus I/O Propagate Register]]
* [[NextReg:$8C]] [[Alternate ROM Register]]
* [[NextReg:$8E]] [[Memory Mapping Register]]
* [[NextReg:$8F]] [[Memory Mapping Mode Register]]
* [[NextReg:$90-$93]] [[Pi GPIO Output Enable Register]]
* [[NextReg:$98-$9B]] [[Pi GPIO Register]]
* [[NextReg:$A0]] [[Pi Peripheral Enable Register]]
* [[NextReg:$A2]] [[Pi I2S Audio Control Register]]
* [[NextReg:$A3]] [[Pi I2S Clock Divide Register]]
* [[NextReg:$A8]] [[ESP WiFi GPIO Output Register]]
* [[NextReg:$A9]] [[ESP WiFi GPIO Register]]
* [[NextReg:$B0]] [[Extended Keys 0 Register]]
* [[NextReg:$B1]] [[Extended Keys 1 Register]]
* [[NextReg:$B2]] [[DivMMC Trap Enable 1 Register]]
* [[NextReg:$B2]] [[Extended MD Pad Buttons Register]]
* [[NextReg:$B4]] [[DivMMC Trap Enable 2 Register]]
* [[NextReg:$B8]] [[Divmmc Entry Points 0]]
* [[NextReg:$B9]] [[Divmmc Entry Points Valid 0]]
* [[NextReg:$BA]] [[Divmmc Entry Points Timing 0]]
* [[NextReg:$BB]] [[Divmmc Entry Points 1]]
* [[NextReg:$C0]] [[Interrupt Control Register]]
* [[NextReg:$C2]] [[NMI Return Address LSB Register]]
* [[NextReg:$C3]] [[NMI Return Address MSB Register]]
* [[NextReg:$C4]] [[Interrupt Enable 0 Register]]
* [[NextReg:$C5]] [[Interrupt Enable 1 Register]]
* [[NextReg:$C6]] [[Interrupt Enable 2 Register]]
* [[NextReg:$C8]] [[Interrupt Status 0 Register]]
* [[NextReg:$C9]] [[Interrupt Status 1 Register]]
* [[NextReg:$CA]] [[Interrupt Status 2 Register]]
* [[NextReg:$CC]] [[DMA interrupt enable 0]]
* [[NextReg:$CD]] [[DMA interrupt enable 1]]
* [[NextReg:$CE]] [[DMA interrupt enable 2]]
* [[NextReg:$D8]] [[I/O Traps Register]]
* [[NextReg:$D9]] [[I/O Trap Write Register]]
* [[NextReg:$DA]] [[I/O Trap Cause Register]]
* [[NextReg:$F0]] [[XDEV command]]
* [[NextReg:$F8]] [[XADC Register]]
* [[NextReg:$F9]] [[XADC D0 Register]]
* [[NextReg:$FA]] [[XADC D1 Register]]
* [[NextReg:$FF]] [[Debug LED Control Register]]

Latest revision as of 08:38, 30 December 2025

This is a general list of ports and registers used to control features of the Spectrum Next.

About The Content of this Page

This page features the list of the Next ports and control registers.

A partial replacement to some of the content that the old codebase provided has been migrated to https://explorer.specnext.dev/ - this site is still under active development, but aims to be an automated way to explore the contents of official specification & documents.

The information is manually copied from the specification, so if something is off or missing, check the gitlab repository of ZX Next FPGA core: ports.txt and nextreg.txt and changelog.md.

Mapped Next Ports

A note on partial decoding

Most Spectrum peripherals did not actually decode all 16 bits of the address bus; they checked only for certain bits, and would respond if those bit values were set correctly, regardless of the other bits. The "bitmask" column for each port shows the bits that are tested for by the device. Traditionally all "unused" bits are set to 1 to avoid conflicts with other devices, which is the basis of the given port numbers; but alternate port numbers may be used in some cases. However, beware of creating clashes: in particular any port which does not intend to access the ULA should have the LSB set, as the ULA checks only for a reset LSB.

It is not known if the Next's built-in devices will have this decoding restriction, but it seems a safe presumption that they will not except where needed by legacy code.

On the other hand, partial decoding can allow use of the multiple output opcodes such as OTIR, which normally places the loop counter on the top half of the address bus - thus making it useless except for devices which ignore this top half. This is the reason why some of the Next registers do ignore the top half of the port address.

The list of ports

The following ports are currently documented in this wiki:

Next/TBBlue Feature Control Registers

Specific features of the Next are controlled via these register numbers, accessed via IO:$243B and IO:$253B, or via the NEXTREG opcode.

The following Next Registers are currently described in this wiki:

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