Pi I2S Clock Divide Register
From SpecNext Wiki
| Number | TBRegisterNumber::$A3 |
|---|---|
| Readable | TBRegisterReadable::Yes |
| Writable | TBRegisterWritable::Yes |
| Short Description | [[ShortDesc:: |
The I2S master-mode was REMOVED in core3.1.5 as well as this register.
bits 7:0 = Clock divide sets sample rate when in master mode (soft reset = decimal 11)
clock divider = 538461 / SampleRateHz - 1
i.e. SampleRateHz = 538461 / (clock divider + 1)
The default value corresponds to ~44871Hz sample rate.