Interrupt Status 0 Register
From SpecNext Wiki
| Number | TBRegisterNumber::$C8 |
|---|---|
| Readable | TBRegisterReadable::Yes |
| Writable | TBRegisterWritable::Yes |
| Short Description | ShortDesc::has interrupt occurred? |
bits 7:2 = Reserved must be 0 bit 1 = Line bit 0 = ULA
- (R) Set bits indicate the device generated an interrupt in the past or an interrupt is pending
- (W) Set bits clear the status. In hw im2 mode the status will continue to read as set until the interrupt pending condition is cleared