Hw im2 mode

hw im2 mode is enabled by the bit 0 of NextReg:$C0.

If not in hw im2 mode, ie normal spectrum behaviour, then all devices that generate an interrupt do it by asserting /int low for around 30 cycles and that's it.

If you are in hw im2 mode, then all interrupting devices including the ula has an im2 state machine attached. If an interrupt is generated, the state machine remembers this as it moves to an assert /int state. Recognition of RETI for the specific device moves the state machine to a place where another /int from the device can be accepted.

For recognition of RETI:

reti instruction has been detected active in T3 for rising edge of T4

so on rising edge of T4, the hw will move to a state where it will see a new int event from the device. /int events are edge detected so you can't hold /int low forever and keep generating interrupts.

That does mean, eg, that if multiple events occur while the isr still hasn't executed RETI then you're not going to see more than the one current int. If the dma is taking a long time, multiple ctc ints on a channel only generates one channel interrupt when the dma ultimately gives up the bus. If you have the ctc interrupting dma op, then you'll see them all most likely