Expansion Bus Decoding b8-15 Register
From SpecNext Wiki
| Next Register Number | $87 |
|---|---|
| Readable | Yes |
| Writable | Yes |
| Short Description | When expansion bus is enabled: Internal ports decoding mask |
| Bit | Description |
|---|---|
| 7 | (bit 15) Masking decoding: NextPort:$123B |
| 6 | (bit 14) Masking decoding: NextPort:$xx57, NextPort:$xx5B and NextPort:$303B |
| 5 | (bit 13) Masking decoding: NextPort:$FADF, NextPort:$FBDF and NextPort:$FFDF |
| 4 | (bit 12) Masking decoding: NextPort:$133B, NextPort:$143B and NextPort:$153B (UART) |
| 3 | (bit 11) Masking decoding: NextPort:$xxE7 and NextPort:$xxEB (SPI) |
| 2 | (bit 10) Masking decoding: NextPort:$103B and NextPort:$113B |
| 1 | (bit 9) Masking decoding: Multiface (two variable ports) |
| 0 | (bit 8) Masking decoding: NextPort:$xxE3 (DivMMC control) |
since core3.1.1: all bits are set to 1 when: soft reset and bit 31 is clear OR hard reset and bit 31 is set (otherwise content is kept intact). All bits are set to 1 upon hard reset.
When the expansion bus is on, the expansion port decoding mask (Next Registers $86-$89) is logically ANDed with the internal enables (Next Registers $82-$85). A zero bit indicates the internal device is disabled.
If the expansion bus is on, this allows I/O cycles for disabled internal ports to propagate to the expansion bus, otherwise corresponding I/O cycles to the expansion bus are filtered.
(note: Next registers with number higher than $7F are inaccessible from Copper code)