Internal Port Decoding b8-15 Register
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(Redirected from NextReg:$83)
| Next Register Number | $83 |
|---|---|
| Readable | Yes |
| Writable | Yes |
| Short Description | Enabling internal ports decoding |
| Bit | Description |
|---|---|
| 7 | (bit 15) Enabling IO:$123B |
| 6 | (bit 14) Enabling IO:$xx57, IO:$xx5B and IO:$303B |
| 5 | (bit 13) Enabling IO:$FADF, IO:$FBDF and IO:$FFDF |
| 4 | (bit 12) Enabling IO:$133B, IO:$143B and IO:$153B (UART) |
| 3 | (bit 11) Enabling IO:$xxE7 and IO:$xxEB (SPI) |
| 2 | (bit 10) Enabling IO:$103B and IO:$113B |
| 1 | (bit 9) Enabling Multiface (two variable ports) |
| 0 | (bit 8) Enabling IO:$xxE3 (DivMMC control) |
since core3.1.1: all bits are set to 1 when: soft reset and bit 31 is set OR hard reset and bit 31 is clear (otherwise content is kept intact). All bits are set to 1 upon soft reset.
The internal port decoding enables always apply.
When the expansion bus is on, the expansion port decoding (Next Registers $86-$89) enables are logically ANDed with the internal enables (Next Registers $82-$85). A zero bit indicates the internal device is disabled.
If the expansion bus is on, this allows I/O cycles for disabled internal ports to propagate to the expansion bus, otherwise corresponding I/O cycles to the expansion bus are filtered.
(note: Next registers with number higher than $7F are inaccessible from Copper code)