Board feature control

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This is a general list of ports and registers used to control features of the Spectrum Next.

About The Content of this Page

This page features the list of the Next ports and control registers.

A partial replacement to some of the content that the old codebase provided has been migrated to https://explorer.specnext.dev/ - this site is still under active development, but aims to be an automated way to explore the contents of official specification & documents.

The information is manually copied from the specification, so if something is off or missing, check the gitlab repository of ZX Next FPGA core: ports.txt and nextreg.txt and changelog.md.

Mapped Next Ports

A note on partial decoding

Most Spectrum peripherals did not actually decode all 16 bits of the address bus; they checked only for certain bits, and would respond if those bit values were set correctly, regardless of the other bits. The "bitmask" column for each port shows the bits that are tested for by the device. Traditionally all "unused" bits are set to 1 to avoid conflicts with other devices, which is the basis of the given port numbers; but alternate port numbers may be used in some cases. However, beware of creating clashes: in particular any port which does not intend to access the ULA should have the LSB set, as the ULA checks only for a reset LSB.

It is not known if the Next's built-in devices will have this decoding restriction, but it seems a safe presumption that they will not except where needed by legacy code.

On the other hand, partial decoding can allow use of the multiple output opcodes such as OTIR, which normally places the loop counter on the top half of the address bus - thus making it useless except for devices which ignore this top half. This is the reason why some of the Next registers do ignore the top half of the port address.

The list of ports

The following ports are currently documented in this wiki:

Next/TBBlue Feature Control Registers

Specific features of the Next are controlled via these register numbers, accessed via IO:$243B and IO:$253B, or via the NEXTREG opcode.

The following Next Registers are currently described in this wiki:

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