Board feature control

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This is a general list of ports and registers used to control features on the Spectrum Next board.

Note that these lists are automatically generated and not directly editable. To edit data on a port or register, visit its page. To add a new port, click here. To add a new register, click here.

Mapped Spectrum Ports

A note on partial decoding

Most Spectrum peripherals did not actually decode all 16 bits of the address bus; they checked only for certain bits, and would respond if those bit values were set correctly, regardless of the other bits. The "bitmask" column for each port shows the bits that are tested for by the device. Traditionally all "unused" bits are set to 1 to avoid conflicts with other devices, which is the basis of the given port numbers; but alternate port numbers may be used in some cases. However, beware of creating clashes: in particular any port which does not intend to access the ULA should have the LSB set, as the ULA checks only for a reset LSB.

It is not known if the Next's built-in devices will have this decoding restriction, but it seems a safe presumption that they will not except where needed by legacy code.

On the other hand, partial decoding can allow use of the multiple output opcodes such as OTIR, which normally places the loop counter on the top half of the address bus - thus making it useless except for devices which ignore this top half. This is the reason why some of the Next registers do ignore the top half of the port address.

 HexadecimalDecimalMaskDescription
Keyboard$**FE254%xxxx xxxx ---- ---0 where only one bit in x is 0Series of specific ports that read keyboard key presses.
I2C clock$103B4155%0001 0000 0011 1011 ??Sets and reads the I2C SCL line.
I2C data$113B4411%0001 0001 0011 1011 ??Sets and reads the I2C SDA line
Layer 2 Access Port$123B4667%0001 0010 0011 1011 ??Enables Layer 2 and controls paging of layer 2 screen into lower memory.
UART TX$133B4923%0001 0011 0011 1011Sends byte to serial port. If read, tells if data in RX buffer
UART RX$143B5179%0001 0100 0011 1011Reads data from serial port, write sets the baudrate
UART Control$153B5435%0001 0101 0011 1011Configuration of UART interfaces
Plus 3 Memory Paging Control$1FFD8189%0001 ---- ---- --0-Controls ROM paging and special paging options from the +2a/+3.
TBBlue Register Select$243B9275%0010 0100 0011 1011Selects active port for TBBlue/Next feature configuration.
TBBlue Register Access$253B9531%0010 0101 0011 1011Reads and/or writes the selected TBBlue control register.
Sprite Status/Slot Select$303B12347%0011 0000 0011 1011 ??Sets active sprite-attribute index and pattern-slot index, reads sprite status.
Memory Paging Control$7FFD32765%01-- ---- ---- --0-Selects active RAM, ROM, and displayed screen.
Sound Chip Register Write$BFFD49149%10-- ---- ---- --0-Writes to the selected register of the selected sound chip.
Next Memory Bank Select$DFFD57341%1101 1111 1111 1101Provides additional bank select bits for extended memory.
Kempston Mouse Buttons$FADF64223%---- ---0 --0- ----Reads buttons on Kempston Mouse.
Kempston Mouse X$FBDF64479%---- -0-1 --0- ----X coordinate of Kempston Mouse, 0-255.
Kempston Mouse Y$FFDF65503%---- -1-1 --0- ----Y coordinate of Kempston Mouse, 0-192.
Turbo Sound Next Control$FFFD65533%11-- ---- ---- --0-Controls stereo channels and selects active sound chip and sound chip channel.
MB02 DMA Port$xx0B11---- ---- 0000 1011Controls Z8410 DMA chip via MB02 standard.
Kempston Joystick$xx1F31%---- ---- 0001 1111Reads movement of joysticks using Kempston interface.
Kempston Joystick 2, Joystick I/O$xx3755Kempston interface second joystick variant and controls joystick I/O.
Sprite Attribute Upload$xx5787%---- ---- 0101 0111Uploads sprite positions, visibility, colour type and effect flags.
Sprite Pattern Upload$xx5B91%---- ---- 0101 1011 ??Used to upload the pattern of the selected sprite.
Datagear DMA Port$xx6B107---- ---- 0110 1011Controls zxnDMA chip
SpecDrum DAC Output$xxDF223%---- ---- --01 1111Output to SpecDrum DAC.
ULA Control Port$xxFE254Controls border color and base Spectrum audio settings.
Timex Sinclair Video Mode Control$xxFF255Controls Timex Sinclair video modes and colours in hi-res mode.

Next/TBBlue Feature Control Registers

Specific features of the Next are controlled via these register numbers, accessed via TBBlue Register Select ($243B / 9275) and TBBlue Register Access ($253B / 9531), or via the NEXTREG opcode.

 NumberReadableWritableDescription
Machine ID Register$00YesNoIdentifies TBBlue board type. Should always be 10 on Next.
Core Version Register$01YesNoIdentifies core (FPGA image) version.
Next Reset Register$02YesYesIdentifies type of last reset. Can be written to force reset.
Machine Type Register$03YesYesIdentifies timing and machine type.
Config Mapping Register$04NoYesIn config mode, allows RAM to be mapped to ROM area.
Peripheral 1 Register$05YesYesSets joystick mode, video frequency and Scandoubler.
Peripheral 2 Register$06YesYesEnables CPU Speed key, DivMMC, Multiface, Mouse and AY audio.
CPU Speed Register$07YesYesSets CPU Speed, reads actual speed.
Peripheral 3 Register$08YesYesABC/ACB Stereo, Internal Speaker, SpecDrum, Timex Video Modes, Turbo Sound Next, RAM contention and [un]lock 128k paging.
Peripheral 4 Register$09YesYesSets scanlines, AY mono output, Sprite-id lockstep, reset DivMMC mapram and disable HDMI audio.
Peripheral 5 Register$0AYesYesMouse buttons and DPI config
Core Version Register (sub minor)$0EYesNoIdentifies core (FPGA image) version (sub minor number).
Anti-brick Register$10YesYesUsed within the Anti-brick system.
Video Timing Register$11YesYesSets video output timing variant.
Layer 2 RAM Page Register$12YesYesSets the bank number where Layer 2 video memory begins.
Layer 2 RAM Shadow Page Register$13YesYesSets the bank number where the Layer 2 shadow screen begins.
Global Transparency Register$14YesYesSets the "transparent" colour for Layer 2, ULA and LoRes pixel data.
Sprite and Layers System Register$15YesYesEnables/disables Sprites and Lores Layer, and chooses priority of sprites and Layer 2.
Layer 2 X Offset Register$16YesYesSets the pixel offset used for drawing Layer 2 graphics on the screen.
Layer 2 Y Offset Register$17YesYesSets the Y offset used when drawing Layer 2 graphics on the screen.
Clip Window Layer 2 Register$18YesYesSets and reads clip-window for Layer 2.
Clip Window Sprites Register$19YesYesSets and reads clip-window for Sprites
Clip Window ULA/LoRes Register$1AYesYesSets and reads clip-window for ULA/LoRes layer.
Clip Window Tilemap Register$1BYesYesSets and reads clip-window for Tilemap.
Clip Window Control Register$1CYesYesControls (resets) the clip-window registers indices.
Active Video Line MSB Register$1EYesNoHolds the MSB (only, as bit 0) of the raster line currently being drawn.
Active Video Line LSB Register$1FYesNoHolds the eight LSBs of the raster line currently being drawn.
Video Line Interrupt Control Register$22YesYesControls the timing of raster interrupts and the ULA frame interrupt.
Video Line Interrupt Value Register$23YesYesHolds the eight LSBs of the line on which a raster interrupt should occur.
ULA X Offset Register$26YesYesPixel X offset (0..255) to use when drawing ULA Layer.
ULA Y Offset Register$27YesYesPixel Y offset (0..191) to use when drawing ULA Layer.
Keymap High Address Register$28YesYesPS/2 Keymap address MSB, read (pending) first byte of palette colour
Keymap Low Address Register$29NoYesPS/2 Keymap address LSB.
Keymap High Data Register$2ANoYesHigh data to PS/2 Keymap (MSB of data in bit 0)
Keymap Low Data Register$2BNoYesLow eight LSBs of PS/2 Keymap data.
DAC B (left) mirror Register$2CYesYesDAC B mirror, read current I2S left MSB
DAC A+D (mono) mirror Register$2DYesYesSpecDrum port 0xDF / DAC A+D mirror, read current I2S LSB
DAC C (right) mirror Register$2EYesYesDAC C mirror, read current I2S right MSB
Tilemap Offset X MSB Register$2FYesYesSets the pixel offset (two high bits) used for drawing Tilemap graphics on the screen.
Tilemap Offset X LSB Register$30YesYesSets the pixel offset (eight low bits) used for drawing Tilemap graphics on the screen.
Tilemap Offset Y Register$31YesYesSets the pixel offset used for drawing Tilemap graphics on the screen.
LoRes X Offset Register$32YesYesPixel X offset (0..255) to use when drawing LoRes Layer.
LoRes Y Offset Register$33YesYesPixel Y offset (0..191) to use when drawing LoRes Layer.
Sprite port-mirror Index Register$34YesYesSelects sprite index 0..127 to be affected by writes to other Sprite ports (and mirrors).
Sprite port-mirror Attribute 0 Register$35NoYesNextreg port-mirror to write directly into "byte 1" of Sprite Attribute Upload ($xx57 / ).
Sprite port-mirror Attribute 1 Register$36NoYesNextreg port-mirror to write directly into "byte 2" of Sprite Attribute Upload ($xx57 / ).
Sprite port-mirror Attribute 2 Register$37NoYesNextreg port-mirror to write directly into "byte 3" of Sprite Attribute Upload ($xx57 / ).
Sprite port-mirror Attribute 3 Register$38NoYesNextreg port-mirror to write directly into "byte 4" of Sprite Attribute Upload ($xx57 / ).
Sprite port-mirror Attribute 4 Register$39NoYesNextreg port-mirror to write directly into "byte 5" of Sprite Attribute Upload ($xx57 / ).
Palette Index Register$40YesYesChooses an palette element (index) to manipulate with
Palette Value Register$41YesYesUse to set/read 8-bit colours of the ULANext palette.
Enhanced ULA Ink Color Mask$42YesYesSpecifies mask to extract ink colour from attribute cell value in ULANext mode.
Enhanced ULA Control Register$43YesYesEnables or disables Enhanced ULA interpretation of attribute values and toggles active palette.
Enhanced ULA Palette Extension$44YesYesUse to set 9-bit (2-byte) colours of the Enhanced ULA palette, or to read second byte of colour.
Transparency colour fallback Register$4AYesYes8-bit colour to be used when all layers contain transparent pixel.
Sprites Transparency Index Register$4BYesYesIndex into sprite palette (of "transparent" colour).
Tilemap Transparency Index Register$4CYesYesIndex into Tilemap palette (of "transparent" colour).
Memory management slot 0 bank$50YesYesSelects the 8k-bank stored in 8k-slot 0 (see Memory map).
Memory management slot 1 bank$51YesYesSelects the 8k-bank stored in 8k-slot 1 (see Memory map).
Memory management slot 2 bank$52YesYesSelects the 8k-bank stored in 8k-slot 2 (see Memory map).
Memory management slot 3 bank$53YesYesSelects the 8k-bank stored in 8k-slot 3 (see Memory map).
Memory management slot 4 bank$54YesYesSelects the 8k-bank stored in 8k-slot 4 (see Memory map).
Memory management slot 5 bank$55YesYesSelects the 8k-bank stored in 8k-slot 5 (see Memory map).
Memory management slot 6 bank$56YesYesSelects the 8k-bank stored in 8k-slot 6 (see Memory map).
Memory management slot 7 bank$57YesYesSelects the 8k-bank stored in 8k-slot 7 (see Memory map).
Copper Data$60NoYesUsed to upload code to the Copper.
Copper Control Low Byte$61YesYesHolds low byte of Copper control bits.
Copper Control High Byte$62YesYesHolds high byte of Copper control flags.
Copper Data 16-bit Write Register$63NoYesUsed to upload code to the Copper.
Vertical Video Line Offset Register$64YesYesOffset numbering of raster lines in copper/interrupt/active register
ULA Control Register$68YesYesDisable ULA, controls ULA mixing/blending, enable ULA+
Display Control 1 Register$69YesYesLayer2, ULA shadow, Timex $FF port
LoRes Control Register$6AYesYesLoRes Radastan mode
Tilemap Control Register$6BYesYesControls Tilemap mode.
Default Tilemap Attribute Register$6CYesYesDefault tile attribute for 8-bit only maps.
Tilemap Base Address Register$6EYesYesBase address of the 40x32 or 80x32 tile map (similar to text-mode of other computers).
Tile Definitions Base Address Register$6FYesYesBase address of the tiles' graphics.
Layer 2 Control Register$70YesYesLayer 2 resolution, palette offset
Layer 2 X Offset MSB Register$71YesYesSets the pixel offset used for drawing Layer 2 graphics on the screen.
Sprite port-mirror Attribute 0 (with INC) Register$75NoYesSame as Sprite port-mirror Attribute 0 Register ($35) (write first byte of sprite-attributes), plus increments Sprite port-mirror Index Register ($34)
Sprite port-mirror Attribute 1 (with INC) Register$76NoYesSame as Sprite port-mirror Attribute 1 Register ($36) (write second byte of sprite-attributes), plus increments Sprite port-mirror Index Register ($34)
Sprite port-mirror Attribute 2 (with INC) Register$77NoYesSame as Sprite port-mirror Attribute 2 Register ($37) (write third byte of sprite-attributes), plus increments Sprite port-mirror Index Register ($34)
Sprite port-mirror Attribute 3 (with INC) Register$78NoYesSame as Sprite port-mirror Attribute 3 Register ($38) (write fourth byte of sprite-attributes), plus increments Sprite port-mirror Index Register ($34)
Sprite port-mirror Attribute 4 (with INC) Register$79NoYesThe same as Sprite port-mirror Attribute 4 Register ($39) (write fifth byte of sprite-attributes), plus increments Sprite port-mirror Index Register ($34)
User Storage 0 Register$7FYesYes8-bit storage for user
Expansion Bus Enable Register$80YesYesExpansion bus enable/config
Expansion Bus Control Register$81YesYesExpansion bus controls
Internal Port Decoding b0-7 Register$82YesYesEnabling internal ports decoding
Internal Port Decoding b8-15 Register$83YesYesEnabling internal ports decoding
Internal Port Decoding b16-23 Register$84YesYesEnabling internal ports decoding
Internal Port Decoding b24-31 Register$85YesYesEnabling internal ports decoding
Expansion Bus Decoding b0-7 Register$86YesYesWhen expansion bus is enabled: Internal ports decoding mask
Expansion Bus Decoding b8-15 Register$87YesYesWhen expansion bus is enabled: Internal ports decoding mask
Expansion Bus Decoding b16-23 Register$88YesYesWhen expansion bus is enabled: Internal ports decoding mask
Expansion Bus Decoding b24-31 Register$89YesYesWhen expansion bus is enabled: Internal ports decoding mask
Expansion Bus I/O Propagate Register$8AYesYesMonitoring internal I/O or adding external keyboard
Alternate ROM$8CYesYesEnable alternate ROM or lock 48k ROM
Memory Mapping Register$8EYesYesControl classic Spectrum memory mapping
Pi GPIO Output Enable Register$90-$93YesYesEnables GPIO pins output
Pi GPIO Register$98-$9BYesYesGPIO pins mapped to Next Register
Pi Peripheral Enable Register$A0YesYesEnable Pi peripherals: UART, Pi hats, I2C, SPI
Pi I2S Audio Control Register$A2YesYesPi I2S controls
Pi I2S Clock Divide Register$A3YesYesPi I2S clock divide in master mode.
ESP WiFi GPIO Output Register$A8YesYesESP WiFi GPIO Output
ESP WiFi GPIO Register$A9YesYesESP WiFi GPIO Read/Write
Extended Keys 0 Register$B0YesNoRead Next keyboard compound keys separately
Extended Keys 1 Register$B1YesNoRead Next keyboard compound keys separately
DivMMC Trap Enable 1 Register$B2YesYesDivMMC trap configuration
DivMMC Trap Enable 2 Register$B4YesYesDivMMC trap configuration
Debug LED Control Register$FFNoYesTurns debug LEDs on and off on TBBlue implementations that have them.