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Property:
TBRegisterWritable
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This is a property of type
Boolean
.
Description
Next HW Register write ability. (en)
Usage
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Showing 119 pages using this property.
M
Memory management slot 0 bank
+
true
+
A
Anti-brick Register
+
true
+
S
Sprite port-mirror Attribute 4 (with INC) Register
+
true
+
L
Layer 2 RAM Page Register
+
true
+
D
Debug LED Control Register
+
true
+
G
Global Transparency Register
+
true
+
C
Clip Window Layer 2 Register
+
true
+
Clip Window Sprites Register
+
true
+
U
ULA Control Register
+
true
+
C
Clip Window ULA/LoRes Register
+
true
+
Clip Window Tilemap Register
+
true
+
Clip Window Control Register
+
true
+
Copper Data
+
true
+
S
Sprite port-mirror Attribute 1 Register
+
true
+
K
Keymap High Address Register
+
true
+
Keymap High Data Register
+
true
+
T
Tilemap Offset X MSB Register
+
true
+
S
Sprites Transparency Index Register
+
true
+
T
Tilemap Offset X LSB Register
+
true
+
D
Default Tilemap Attribute Register
+
true
+
S
Sprite port-mirror Attribute 0 Register
+
true
+
T
Tilemap Transparency Index Register
+
true
+
S
Sprite port-mirror Attribute 2 Register
+
true
+
T
Tile Definitions Base Address Register
+
true
+
S
Sprite port-mirror Attribute 3 Register
+
true
+
P
Palette Value Register
+
true
+
T
Tilemap Control Register
+
true
+
M
Memory management slot 1 bank
+
true
+
Memory management slot 2 bank
+
true
+
Memory management slot 3 bank
+
true
+
Memory management slot 4 bank
+
true
+
Memory management slot 5 bank
+
true
+
C
Copper Control Low Byte
+
true
+
Copper Control High Byte
+
true
+
T
Tilemap Base Address Register
+
true
+
S
Sprite port-mirror Attribute 0 (with INC) Register
+
true
+
Sprite port-mirror Attribute 2 (with INC) Register
+
true
+
Sprite port-mirror Attribute 3 (with INC) Register
+
true
+
P
Peripheral 1 Register
+
true
+
E
Enhanced ULA Control Register
+
true
+
Enhanced ULA Ink Color Mask
+
true
+
Enhanced ULA Palette Extension
+
true
+
U
ULA X Offset Register
+
true
+
ULA Y Offset Register
+
true
+
D
DAC B (left) mirror Register
+
true
+
DAC A+D (mono) mirror Register
+
true
+
DAC C (right) mirror Register
+
true
+
L
LoRes X Offset Register
+
true
+
LoRes Y Offset Register
+
true
+
C
Copper Data 16-bit Write Register
+
true
+
D
Display Control 1 Register
+
true
+
L
LoRes Control Register
+
true
+
U
User Storage 0 Register
+
true
+
E
Expansion Bus Control Register
+
true
+
I
Internal Port Decoding b0-7 Register
+
true
+
Internal Port Decoding b8-15 Register
+
true
+
Internal Port Decoding b16-23 Register
+
true
+
Internal Port Decoding b24-31 Register
+
true
+
E
Expansion Bus Decoding b0-7 Register
+
true
+
Expansion Bus Decoding b8-15 Register
+
true
+
Expansion Bus Decoding b16-23 Register
+
true
+
Expansion Bus Decoding b24-31 Register
+
true
+
Expansion Bus I/O Propagate Register
+
true
+
P
Pi GPIO Output Enable Register
+
true
+
Pi GPIO Register
+
true
+
Pi Peripheral Enable Register
+
true
+
Pi I2S Audio Control Register
+
true
+
Pi I2S Clock Divide Register
+
true
+
A
Alternate ROM
+
true
+
E
Expansion Bus Enable Register
+
true
+
L
Layer 2 Control Register
+
true
+
Layer 2 X Offset MSB Register
+
true
+
E
ESP WiFi GPIO Output Register
+
true
+
ESP WiFi GPIO Register
+
true
+
D
DivMMC Trap Enable 1 Register
+
true
+
DivMMC Trap Enable 2 Register
+
true
+
M
Memory Mapping Register
+
true
+
E
Extended Keys 0 Register
+
false
+
Extended Keys 1 Register
+
false
+
P
Peripheral 5 Register
+
true
+
A
Active Video Line MSB Register
+
false
+
Active Video Line LSB Register
+
false
+
V
Video Line Interrupt Control Register
+
true
+
Video Line Interrupt Value Register
+
true
+
Vertical Video Line Offset Register
+
true
+
C
Core Version Register
+
false
+
Core Version Register (sub minor)
+
false
+
CPU Speed Register
+
true
+
Config Mapping Register
+
true
+
S
Sprite and Layers System Register
+
true
+
J
Joystick I/O Mode
+
true
+
B
Board ID
+
false
+
G
Generate Maskable Interrupt
+
true
+
R
Reserved
+
false
+
M
Memory Mapping Mode
+
true
+
E
Extended MD Pad Buttons
+
false
+
D
Divmmc Entry Points 0
+
true
+
Divmmc Entry Points Valid 0
+
true
+
Divmmc Entry Points Timing 0
+
true
+
Divmmc Entry Points 1
+
true
+
I
Interrupt Control
+
true
+
N
NMI Return Address LSB
+
true
+
NMI Return Address MSB
+
true
+
I
Interrupt Enable 0
+
true
+
Interrupt Enable 1
+
true
+
Interrupt Enable 2
+
true
+
Interrupt Status 0
+
true
+
Interrupt Status 1
+
true
+
Interrupt Status 2
+
true
+
D
DMA interrupt enable 0
+
true
+
DMA interrupt enable 1
+
true
+
DMA interrupt enable 2
+
true
+
I
I/O Traps
+
true
+
I/O Trap Write
+
true
+
I/O Trap Cause
+
false
+
X
XDEV command
+
true
+
XADC register
+
true
+
XADC D0
+
true
+
XADC D1
+
true
+
This is a property of type
Boolean
.
Description
Next HW Register write ability. (en)
Edit Property