User contributions for Ped7g
6 December 2019
- 21:5621:56, 6 December 2019 diff hist +70 Sprite port-mirror Index Register read register detail extended by info from Allen current
5 December 2019
- 00:2600:26, 5 December 2019 diff hist +55 Machine Type Register core 3.0.5 changes/refresh
- 00:2000:20, 5 December 2019 diff hist +264 CPU Speed Register core 3.0.5 changes/refresh
- 00:1300:13, 5 December 2019 diff hist +52 Peripheral 4 Setting Register core 3.0.5 changes/refresh
- 00:0700:07, 5 December 2019 diff hist −493 Expansion Bus Control Register core 3.0.5 changes/refresh
4 December 2019
- 23:5823:58, 4 December 2019 diff hist −373 Expansion Bus Enable Register core 3.0.5 changes/refresh
- 23:5323:53, 4 December 2019 diff hist +996 m Expansion Bus Control Register core 3.0.5 changes/refresh Tag: Removed redirect
- 23:5223:52, 4 December 2019 diff hist 0 m Expansion Bus Enable Register core 3.0.5 changes/refresh
- 23:5023:50, 4 December 2019 diff hist 0 Expansion Bus Enable Register core 3.0.5 changes/refresh
- 23:4823:48, 4 December 2019 diff hist +43 N Expansion Bus Control Register Ped7g moved page Expansion Bus Control Register to Expansion Bus Enable Register: core 3.0.5 change/refresh Tag: New redirect
- 23:4823:48, 4 December 2019 diff hist 0 m Expansion Bus Enable Register Ped7g moved page Expansion Bus Control Register to Expansion Bus Enable Register: core 3.0.5 change/refresh
- 23:4623:46, 4 December 2019 diff hist +27 m Alternate ROM Register No edit summary
- 23:4523:45, 4 December 2019 diff hist +711 N Alternate ROM Register core 3.0.5 changes/refresh
2 December 2019
- 21:1421:14, 2 December 2019 diff hist +318 Memory Paging Control core 3.0 changes/refresh
- 20:5120:51, 2 December 2019 diff hist +359 File Formats SNA vs new NextZXOS info
- 20:4420:44, 2 December 2019 diff hist +28 Peripheral 3 Setting Register core 3.0 changes/refresh
- 20:3620:36, 2 December 2019 diff hist +333 Peripheral 3 Setting Register core 3.0 changes/refresh
1 December 2019
- 06:2106:21, 1 December 2019 diff hist −7 Memory Paging Control core 3.0 changes/refresh
- 01:0001:00, 1 December 2019 diff hist +96 Layer 2 Shadow RAM bank Register core 3.0 changes/refresh
- 00:5900:59, 1 December 2019 diff hist +96 Layer 2 Active RAM Bank Register core 3.0 changes/refresh
28 November 2019
- 04:2004:20, 28 November 2019 diff hist −12 Memory map core 3.0 changes/refresh
27 November 2019
- 20:1720:17, 27 November 2019 diff hist +378 Layer 2 Access Port core 3.0 changes/refresh
- 17:5917:59, 27 November 2019 diff hist +56 m Layer 2 core 3.0 changes/refresh
- 17:3517:35, 27 November 2019 diff hist +13 m Layer 2 core 3.0 changes/refresh
- 17:2917:29, 27 November 2019 diff hist +1,286 Layer 2 core 3.0 changes/refresh
16 November 2019
- 10:3610:36, 16 November 2019 diff hist +115 Assemblers updating sjasmplus description with new features from v1.14.3
12 November 2019
- 17:3017:30, 12 November 2019 diff hist +1 m Pi I2S Clock Divide Register No edit summary
- 17:3017:30, 12 November 2019 diff hist +50 Pi I2S Clock Divide Register fixing default value Hz result... (my math, argh)
- 12:3912:39, 12 November 2019 diff hist +289 N Pi I2S Clock Divide Register core 3.0 changes/refresh
- 12:3312:33, 12 November 2019 diff hist +723 N Pi I2S Audio Control Register core 3.0 changes/refresh
- 12:1712:17, 12 November 2019 diff hist +675 N Pi Peripheral Enable Register core 3.0 changes/refresh
- 11:5411:54, 12 November 2019 diff hist +580 N Pi GPIO Register core 3.0 changes/refresh current
- 11:5011:50, 12 November 2019 diff hist +86 m Pi GPIO Output Enable Register core 3.0 changes/refresh current
- 11:4811:48, 12 November 2019 diff hist +450 N Pi GPIO Output Enable Register core 3.0 changes/refresh
- 11:4211:42, 12 November 2019 diff hist +1,097 N Expansion Bus I/O Propagate Register core 3.0 changes/refresh
- 11:2811:28, 12 November 2019 diff hist +860 N Expansion Bus Decoding b24-31 Register core 3.0 changes/refresh
- 11:2611:26, 12 November 2019 diff hist +21 Internal Port Decoding b24-31 Register core 3.0 changes/refresh
- 11:2211:22, 12 November 2019 diff hist +1,476 N Expansion Bus Decoding b16-23 Register core 3.0 changes/refresh
- 10:4210:42, 12 November 2019 diff hist +1,330 N Expansion Bus Decoding b8-15 Register core 3.0 changes/refresh
- 10:3910:39, 12 November 2019 diff hist +1,100 N Expansion Bus Decoding b0-7 Register core 3.0 changes/refresh
- 10:1610:16, 12 November 2019 diff hist +453 Internal Port Decoding b24-31 Register core 3.0 changes/refresh
- 10:1610:16, 12 November 2019 diff hist +453 Internal Port Decoding b16-23 Register core 3.0 changes/refresh
- 10:1510:15, 12 November 2019 diff hist +453 Internal Port Decoding b8-15 Register core 3.0 changes/refresh
- 10:1410:14, 12 November 2019 diff hist +453 Internal Port Decoding b0-7 Register core 3.0 changes/refresh
- 10:0710:07, 12 November 2019 diff hist +9 m Internal Port Decoding b0-7 Register core 3.0 changes/refresh
- 10:0710:07, 12 November 2019 diff hist +9 m Internal Port Decoding b8-15 Register core 3.0 changes/refresh
- 10:0510:05, 12 November 2019 diff hist +404 N Internal Port Decoding b24-31 Register core 3.0 changes/refresh
- 10:0010:00, 12 November 2019 diff hist +978 N Internal Port Decoding b16-23 Register core 3.0 changes/refresh
- 09:4909:49, 12 November 2019 diff hist +823 N Internal Port Decoding b8-15 Register core 3.0 changes/refresh
- 09:3609:36, 12 November 2019 diff hist +593 N Internal Port Decoding b0-7 Register core 3.0 changes/refresh