User contributions for Ped7g

19:4419:44, 2 December 2019 diff hist +28 Peripheral 3 Setting Register core 3.0 changes/refresh
19:3619:36, 2 December 2019 diff hist +333 Peripheral 3 Setting Register core 3.0 changes/refresh

05:2105:21, 1 December 2019 diff hist −7 Memory Paging Control core 3.0 changes/refresh
00:0000:00, 1 December 2019 diff hist +96 Layer 2 Shadow RAM bank Register core 3.0 changes/refresh

23:5923:59, 30 November 2019 diff hist +96 Layer 2 Active RAM Bank Register core 3.0 changes/refresh

03:2003:20, 28 November 2019 diff hist −12 Memory map core 3.0 changes/refresh

19:1719:17, 27 November 2019 diff hist +378 Layer 2 Access Port core 3.0 changes/refresh
16:5916:59, 27 November 2019 diff hist +56 m Layer 2 core 3.0 changes/refresh
16:3516:35, 27 November 2019 diff hist +13 m Layer 2 core 3.0 changes/refresh
16:2916:29, 27 November 2019 diff hist +1,286 Layer 2 core 3.0 changes/refresh

09:3609:36, 16 November 2019 diff hist +115 Assemblers updating sjasmplus description with new features from v1.14.3

16:3016:30, 12 November 2019 diff hist +1 m Pi I2S Clock Divide Register No edit summary
16:3016:30, 12 November 2019 diff hist +50 Pi I2S Clock Divide Register fixing default value Hz result... (my math, argh)
11:3911:39, 12 November 2019 diff hist +289 N Pi I2S Clock Divide Register core 3.0 changes/refresh
11:3311:33, 12 November 2019 diff hist +723 N Pi I2S Audio Control Register core 3.0 changes/refresh
11:1711:17, 12 November 2019 diff hist +675 N Pi Peripheral Enable Register core 3.0 changes/refresh
10:5410:54, 12 November 2019 diff hist +580 N Pi GPIO Register core 3.0 changes/refresh current
10:5010:50, 12 November 2019 diff hist +86 m Pi GPIO Output Enable Register core 3.0 changes/refresh current
10:4810:48, 12 November 2019 diff hist +450 N Pi GPIO Output Enable Register core 3.0 changes/refresh
10:4210:42, 12 November 2019 diff hist +1,097 N Expansion Bus I/O Propagate Register core 3.0 changes/refresh
10:2810:28, 12 November 2019 diff hist +860 N Expansion Bus Decoding b24-31 Register core 3.0 changes/refresh
10:2610:26, 12 November 2019 diff hist +21 Internal Port Decoding b24-31 Register core 3.0 changes/refresh
10:2210:22, 12 November 2019 diff hist +1,476 N Expansion Bus Decoding b16-23 Register core 3.0 changes/refresh
09:4209:42, 12 November 2019 diff hist +1,330 N Expansion Bus Decoding b8-15 Register core 3.0 changes/refresh
09:3909:39, 12 November 2019 diff hist +1,100 N Expansion Bus Decoding b0-7 Register core 3.0 changes/refresh
09:1609:16, 12 November 2019 diff hist +453 Internal Port Decoding b24-31 Register core 3.0 changes/refresh
09:1609:16, 12 November 2019 diff hist +453 Internal Port Decoding b16-23 Register core 3.0 changes/refresh
09:1509:15, 12 November 2019 diff hist +453 Internal Port Decoding b8-15 Register core 3.0 changes/refresh
09:1409:14, 12 November 2019 diff hist +453 Internal Port Decoding b0-7 Register core 3.0 changes/refresh
09:0709:07, 12 November 2019 diff hist +9 m Internal Port Decoding b0-7 Register core 3.0 changes/refresh
09:0709:07, 12 November 2019 diff hist +9 m Internal Port Decoding b8-15 Register core 3.0 changes/refresh
09:0509:05, 12 November 2019 diff hist +404 N Internal Port Decoding b24-31 Register core 3.0 changes/refresh
09:0009:00, 12 November 2019 diff hist +978 N Internal Port Decoding b16-23 Register core 3.0 changes/refresh
08:4908:49, 12 November 2019 diff hist +823 N Internal Port Decoding b8-15 Register core 3.0 changes/refresh
08:3608:36, 12 November 2019 diff hist +593 N Internal Port Decoding b0-7 Register core 3.0 changes/refresh
08:2508:25, 12 November 2019 diff hist +1,046 N Expansion Bus Enable Register core 3.0 changes/refresh
08:1608:16, 12 November 2019 diff hist +37 N Uncommited User Storage Ped7g moved page Uncommited User Storage to User Storage 0 Register: core 3.0 change/refresh current Tag: New redirect
08:1608:16, 12 November 2019 diff hist 0 m User Storage 0 Register Ped7g moved page Uncommited User Storage to User Storage 0 Register: core 3.0 change/refresh current
07:2807:28, 12 November 2019 diff hist +31 LoRes Control Register core 3.0 changes/refresh current
07:2607:26, 12 November 2019 diff hist +93 Tile Definitions Base Address Register core 3.0 changes/refresh
07:2407:24, 12 November 2019 diff hist +94 Tilemap Base Address Register core 3.0 changes/refresh
07:1907:19, 12 November 2019 diff hist +132 Default Tilemap Attribute Register core 3.0 changes/refresh
07:1607:16, 12 November 2019 diff hist −17 Tilemap Control Register core 3.0 changes/refresh
07:0807:08, 12 November 2019 diff hist +366 N LoRes Control Register core 3.0 changes/refresh
07:0407:04, 12 November 2019 diff hist +341 N Display Control 1 Register core 3.0 changes/refresh
06:5606:56, 12 November 2019 diff hist +123 ULA Control Register core 3.0 changes/refresh

22:0722:07, 11 November 2019 diff hist +762 N Copper Data 16-bit Write Register core 3.0 changes/refresh current
21:3821:38, 11 November 2019 diff hist +77 Palette Index Register core 3.0 changes/refresh current
19:5319:53, 11 November 2019 diff hist −17 User Storage 0 Register core 3.0 changes/refresh
16:1616:16, 11 November 2019 diff hist +209 Keymap High Address Register core 3.0 changes/refresh

User contributions for Ped7g

2 December 2019

1 December 2019

30 November 2019

28 November 2019

27 November 2019

16 November 2019

12 November 2019

11 November 2019