User contributions for Sol HSA - SpecNext Wiki

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A user with 94 edits. Account created on 22 May 2020.

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14:5714:57, 7 October 2025 diff hist −232 Circuit Diagrams gallerize images current
14:4714:47, 7 October 2025 diff hist −11 GPIO Socket (J15) gallerize images current
14:4614:46, 7 October 2025 diff hist −31 RTC gallerize images current
14:3914:39, 7 October 2025 diff hist −64 Extended Z80 instruction set link fixes current
14:3414:34, 7 October 2025 diff hist +12 m Emulators linkify known bugs
14:3014:30, 7 October 2025 diff hist −20 m Emulators remove emulatorlisttop
14:2814:28, 7 October 2025 diff hist +8 m Emulators couple empty cells
12:5312:53, 7 October 2025 diff hist −991 Emulators rebuilt tables
12:1812:18, 7 October 2025 diff hist −4 m Extended Z80 instruction set remove one }}
11:5811:58, 7 October 2025 diff hist −1,368 Extended Z80 instruction set removed margin:auto
11:5711:57, 7 October 2025 diff hist +1,011 Extended Z80 instruction set rebuilt tables

10:0510:05, 8 September 2025 diff hist +136 File Formats loadable directory current

14:1014:10, 15 March 2025 diff hist +363 Palettes added alternative rgb values
14:0714:07, 15 March 2025 diff hist +68 N File:256-palette-2.png No edit summary

12:5012:50, 20 February 2025 diff hist +59 Refresh Rates No edit summary current

13:1413:14, 3 November 2024 diff hist +283 N AY Info updated to 78a6ee50 current
13:1113:11, 3 November 2024 diff hist +495 Turbo Sound Next Control updated to 78a6ee50 current
13:0713:07, 3 November 2024 diff hist +394 N Pentagon 1024 paging updated to 78a6ee50 current
13:0313:03, 3 November 2024 diff hist +27 Memory Paging Control updated to 78a6ee50 current
13:0013:00, 3 November 2024 diff hist +193 Keyboard updated to 78a6ee50 current
12:5212:52, 3 November 2024 diff hist +202 N XADC D1 Register updated to 78a6ee50
12:5112:51, 3 November 2024 diff hist +203 N XADC D0 Register updated to 78a6ee50
12:5012:50, 3 November 2024 diff hist +364 N XADC Register updated to 78a6ee50
12:4912:49, 3 November 2024 diff hist +1,545 N XDEV command updated to 78a6ee50 current
12:4712:47, 3 November 2024 diff hist +301 N I/O Trap Cause Register updated to 78a6ee50
12:4112:41, 3 November 2024 diff hist +131 N I/O Trap Write Register updated to 78a6ee50
12:4012:40, 3 November 2024 diff hist +349 N I/O Traps Register updated to 78a6ee50
12:3712:37, 3 November 2024 diff hist +168 DMA interrupt enable 2 updated to 78a6ee50 current
12:3512:35, 3 November 2024 diff hist +168 DMA interrupt enable 1 updated to 78a6ee50 current
12:3412:34, 3 November 2024 diff hist +168 DMA interrupt enable 0 updated to 78a6ee50 current
12:3312:33, 3 November 2024 diff hist +512 N DMA interrupt enable 2 updated to 78a6ee50
12:3212:32, 3 November 2024 diff hist +463 N DMA interrupt enable 1 updated to 78a6ee50
12:3112:31, 3 November 2024 diff hist +262 N DMA interrupt enable 0 updated to 78a6ee50
12:2912:29, 3 November 2024 diff hist +615 N Interrupt Status 2 Register updated to 78a6ee50
12:2812:28, 3 November 2024 diff hist +571 N Interrupt Status 1 Register updated to 78a6ee50
12:2712:27, 3 November 2024 diff hist +388 N Interrupt Status 0 Register updated to 78a6ee50
12:2512:25, 3 November 2024 diff hist +504 N Interrupt Enable 2 Register updated to 78a6ee50
12:2312:23, 3 November 2024 diff hist +419 N Interrupt Enable 1 Register updated to 78a6ee50
12:2212:22, 3 November 2024 diff hist +381 N Interrupt Enable 0 Register updated to 78a6ee50
12:2012:20, 3 November 2024 diff hist +209 N NMI Return Address MSB Register updated to 78a6ee50
12:1912:19, 3 November 2024 diff hist +209 N NMI Return Address LSB Register updated to 78a6ee50
12:1712:17, 3 November 2024 diff hist +1,112 N Interrupt Control Register updated to 78a6ee50
12:1112:11, 3 November 2024 diff hist +1,031 N Divmmc Entry Points 1 Created page with "{{NextRegister |Number=$BB |Readable=Yes |Writable=Yes |ShortDesc=DivMMC automap control }} bit 7 = 1 to enable automap on addresses 0x3DXX (instruction fetch, instant, ROM3..." current
12:0912:09, 3 November 2024 diff hist +550 N Divmmc Entry Points Timing 0 updated to 78a6ee50 current
12:0712:07, 3 November 2024 diff hist +755 N Divmmc Entry Points Valid 0 updated to 78a6ee50 current
12:0512:05, 3 November 2024 diff hist +790 N Divmmc Entry Points 0 updated to 78a6ee50 current
12:0112:01, 3 November 2024 diff hist +387 N Extended MD Pad Buttons Register updated to 78a6ee50
11:5611:56, 3 November 2024 diff hist +83 Extended Keys 1 Register updated to 78a6ee50 current
11:5611:56, 3 November 2024 diff hist +82 Extended Keys 0 Register updated to 78a6ee50 current
11:5411:54, 3 November 2024 diff hist +91 Pi Peripheral Enable Register updated to 78a6ee50 current

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