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A user with 12 edits. Account created on 14 April 2019.

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10:0010:00, 14 April 2019 diff hist 0 m Sprite port-mirror Index Register 4 revisions imported
10:0010:00, 14 April 2019 diff hist 0 m Sprite Attribute 4 Register 3 revisions imported
10:0010:00, 14 April 2019 diff hist 0 m Sprite Attribute 4 (with INC) Register 3 revisions imported
10:0010:00, 14 April 2019 diff hist 0 m Sprite Attribute 3 Register 1 revision imported
10:0010:00, 14 April 2019 diff hist 0 m Sprite Attribute 3 (with INC) Register 2 revisions imported
10:0010:00, 14 April 2019 diff hist 0 m Sprite Attribute 2 Register 2 revisions imported
10:0010:00, 14 April 2019 diff hist 0 m Sprite Attribute 2 (with INC) Register 3 revisions imported
10:0010:00, 14 April 2019 diff hist 0 m Sprite Attribute 1 Register 1 revision imported
10:0010:00, 14 April 2019 diff hist 0 m Sprite Attribute 1 (with INC) Register 2 revisions imported
10:0010:00, 14 April 2019 diff hist 0 m Sprite Attribute 0 Register 2 revisions imported
10:0010:00, 14 April 2019 diff hist 0 m Sprite Attribute 0 (with INC) Register 2 revisions imported
10:0010:00, 14 April 2019 diff hist 0 m Sprite Status/Slot Select 13 revisions imported
10:0010:00, 14 April 2019 diff hist 0 m Sprite Pattern Upload 7 revisions imported
10:0010:00, 14 April 2019 diff hist 0 m Sprite and Layers System Register 13 revisions imported
10:0010:00, 14 April 2019 diff hist 0 m Sprite Attribute Upload 10 revisions imported
10:0010:00, 14 April 2019 diff hist 0 m SpecDrum DAC Output 2 revisions imported
10:0010:00, 14 April 2019 diff hist 0 m Sound Chip Register Write 6 revisions imported
10:0010:00, 14 April 2019 diff hist 0 m DAC A+D Mirror (mono) Register 3 revisions imported
10:0010:00, 14 April 2019 diff hist 0 m Reference machines 3 revisions imported
10:0010:00, 14 April 2019 diff hist 0 m Active Video Line (MSB) Register 5 revisions imported
10:0010:00, 14 April 2019 diff hist 0 m Active Video Line (LSB) Register 6 revisions imported
10:0010:00, 14 April 2019 diff hist 0 m Video Line Interrupt Value Register 5 revisions imported
10:0010:00, 14 April 2019 diff hist 0 m Video Line Interrupt Control Register 7 revisions imported
10:0010:00, 14 April 2019 diff hist 0 m RPi0 Acceleration 3 revisions imported
10:0010:00, 14 April 2019 diff hist 0 m Config Mapping Register 2 revisions imported
10:0010:00, 14 April 2019 diff hist 0 m Plus 3 Memory Paging Control 8 revisions imported
10:0010:00, 14 April 2019 diff hist 0 m Peripheral 4 Setting Register 6 revisions imported
10:0010:00, 14 April 2019 diff hist 0 m Peripheral 3 Setting Register 7 revisions imported
10:0010:00, 14 April 2019 diff hist 0 m Peripheral 2 Setting Register 7 revisions imported
10:0010:00, 14 April 2019 diff hist 0 m Peripheral 1 Setting Register 7 revisions imported
10:0010:00, 14 April 2019 diff hist 0 m Palettes 4 revisions imported
10:0010:00, 14 April 2019 diff hist 0 m Palette Value (8 bit colour) Register 4 revisions imported
10:0010:00, 14 April 2019 diff hist 0 m Palette Index Register 6 revisions imported
10:0010:00, 14 April 2019 diff hist 0 m Core Version Register (sub minor) 1 revision imported
10:0010:00, 14 April 2019 diff hist 0 m Core Version Register 6 revisions imported
10:0010:00, 14 April 2019 diff hist 0 m Reset Register 9 revisions imported
10:0010:00, 14 April 2019 diff hist 0 m Next Memory Bank Select 3 revisions imported
10:0010:00, 14 April 2019 diff hist 0 m NextZXOS 4 revisions imported
10:0010:00, 14 April 2019 diff hist 0 m NextOS 1 revision imported current
10:0010:00, 14 April 2019 diff hist 0 m NextBASIC 14 revisions imported
10:0010:00, 14 April 2019 diff hist 0 m NEX file format 9 revisions imported
10:0010:00, 14 April 2019 diff hist 0 m Memory map 52 revisions imported
10:0010:00, 14 April 2019 diff hist 0 m MMU slot 7 Register 1 revision imported
10:0010:00, 14 April 2019 diff hist 0 m MMU slot 6 Register 1 revision imported
10:0010:00, 14 April 2019 diff hist 0 m MMU slot 5 Register 1 revision imported
10:0010:00, 14 April 2019 diff hist 0 m MMU slot 4 Register 1 revision imported
10:0010:00, 14 April 2019 diff hist 0 m MMU slot 3 Register 1 revision imported
10:0010:00, 14 April 2019 diff hist 0 m MMU slot 2 Register 1 revision imported
10:0010:00, 14 April 2019 diff hist 0 m MMU slot 1 Register 1 revision imported
10:0010:00, 14 April 2019 diff hist 0 m MMU slot 0 Register 1 revision imported

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