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 NumberReadableWritableDescription
Machine Type Register$03YesYesIdentifies timing and machine type.
Memory Mapping Register$8EYesYesControl classic Spectrum memory mapping
Memory management slot 0 bank$50YesYesSelects the 8k-bank stored in 8k-slot 0 (see Memory map).
Memory management slot 1 bank$51YesYesSelects the 8k-bank stored in 8k-slot 1 (see Memory map).
Memory management slot 2 bank$52YesYesSelects the 8k-bank stored in 8k-slot 2 (see Memory map).
Memory management slot 3 bank$53YesYesSelects the 8k-bank stored in 8k-slot 3 (see Memory map).
Memory management slot 4 bank$54YesYesSelects the 8k-bank stored in 8k-slot 4 (see Memory map).
Memory management slot 5 bank$55YesYesSelects the 8k-bank stored in 8k-slot 5 (see Memory map).
Memory management slot 6 bank$56YesYesSelects the 8k-bank stored in 8k-slot 6 (see Memory map).
Memory management slot 7 bank$57YesYesSelects the 8k-bank stored in 8k-slot 7 (see Memory map).
Next Reset Register$02YesYesIdentifies type of last reset. Can be written to force reset.
Palette Index Register$40YesYesChooses an palette element (index) to manipulate with
Palette Value Register$41YesYesUse to set/read 8-bit colours of the ULANext palette.
Peripheral 1 Register$05YesYesSets joystick mode, video frequency and Scandoubler.
Peripheral 2 Register$06YesYesEnables CPU Speed key, DivMMC, Multiface, Mouse and AY audio.
Peripheral 3 Register$08YesYesABC/ACB Stereo, Internal Speaker, SpecDrum, Timex Video Modes, Turbo Sound Next, RAM contention and [un]lock 128k paging.
Peripheral 4 Register$09YesYesSets scanlines, AY mono output, Sprite-id lockstep, reset DivMMC mapram and disable HDMI audio.
Peripheral 5 Register$0AYesYesMouse buttons and DPI config
Pi GPIO Output Enable Register$90-$93YesYesEnables GPIO pins output
Pi GPIO Register$98-$9BYesYesGPIO pins mapped to Next Register
Pi I2S Audio Control Register$A2YesYesPi I2S controls
Pi I2S Clock Divide Register$A3YesYesPi I2S clock divide in master mode.
Pi Peripheral Enable Register$A0YesYesEnable Pi peripherals: UART, Pi hats, I2C, SPI
Sprite and Layers System Register$15YesYesEnables/disables Sprites and Lores Layer, and chooses priority of sprites and Layer 2.
Sprite port-mirror Attribute 0 (with INC) Register$75NoYesSame as Sprite port-mirror Attribute 0 Register ($35) (write first byte of sprite-attributes), plus increments Sprite port-mirror Index Register ($34)
Sprite port-mirror Attribute 0 Register$35NoYesNextreg port-mirror to write directly into "byte 1" of Sprite Attribute Upload ($xx57 / 87).
Sprite port-mirror Attribute 1 (with INC) Register$76NoYesSame as Sprite port-mirror Attribute 1 Register ($36) (write second byte of sprite-attributes), plus increments Sprite port-mirror Index Register ($34)
Sprite port-mirror Attribute 1 Register$36NoYesNextreg port-mirror to write directly into "byte 2" of Sprite Attribute Upload ($xx57 / 87).
Sprite port-mirror Attribute 2 (with INC) Register$77NoYesSame as Sprite port-mirror Attribute 2 Register ($37) (write third byte of sprite-attributes), plus increments Sprite port-mirror Index Register ($34)
Sprite port-mirror Attribute 2 Register$37NoYesNextreg port-mirror to write directly into "byte 3" of Sprite Attribute Upload ($xx57 / 87).
Sprite port-mirror Attribute 3 (with INC) Register$78NoYesSame as Sprite port-mirror Attribute 3 Register ($38) (write fourth byte of sprite-attributes), plus increments Sprite port-mirror Index Register ($34)
Sprite port-mirror Attribute 3 Register$38NoYesNextreg port-mirror to write directly into "byte 4" of Sprite Attribute Upload ($xx57 / 87).
Sprite port-mirror Attribute 4 (with INC) Register$79NoYesThe same as Sprite port-mirror Attribute 4 Register ($39) (write fifth byte of sprite-attributes), plus increments Sprite port-mirror Index Register ($34)
Sprite port-mirror Attribute 4 Register$39NoYesNextreg port-mirror to write directly into "byte 5" of Sprite Attribute Upload ($xx57 / 87).
Sprite port-mirror Index Register$34YesYesSelects sprite index 0..127 to be affected by writes to other Sprite ports (and mirrors).
Sprites Transparency Index Register$4BYesYesIndex into sprite palette (of "transparent" colour).
Tile Definitions Base Address Register$6FYesYesBase address of the tiles' graphics.
Tilemap Base Address Register$6EYesYesBase address of the 40x32 or 80x32 tile map (similar to text-mode of other computers).
Tilemap Control Register$6BYesYesControls Tilemap mode.
Tilemap Offset X LSB Register$30YesYesSets the pixel offset (eight low bits) used for drawing Tilemap graphics on the screen.
Tilemap Offset X MSB Register$2FYesYesSets the pixel offset (two high bits) used for drawing Tilemap graphics on the screen.
Tilemap Offset Y Register$31YesYesSets the pixel offset used for drawing Tilemap graphics on the screen.
Tilemap Transparency Index Register$4CYesYesIndex into Tilemap palette (of "transparent" colour).
Transparency colour fallback Register$4AYesYes8-bit colour to be used when all layers contain transparent pixel.
ULA Control Register$68YesYesDisable ULA, controls ULA mixing/blending, enable ULA+
ULA X Offset Register$26YesYesPixel X offset (0..255) to use when drawing ULA Layer.
ULA Y Offset Register$27YesYesPixel Y offset (0..191) to use when drawing ULA Layer.
User Storage 0 Register$7FYesYes8-bit storage for user
Vertical Video Line Offset Register$64YesYesOffset numbering of raster lines in copper/interrupt/active register
Video Line Interrupt Control Register$22YesYesControls the timing of raster interrupts and the ULA frame interrupt.
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