DMA interrupt enable 0: Difference between revisions
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updated to 78a6ee50 |
linking hw im2 |
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| Line 8: | Line 8: | ||
bit 1 = Line | bit 1 = Line | ||
bit 0 = ULA | bit 0 = ULA | ||
* Set bits indicate the corresponding interrupt will interrupt a dma operation when in hw im2 mode | * Set bits indicate the corresponding interrupt will interrupt a dma operation when in [[hw im2 mode]] | ||
Soft reset = 0x00 | Soft reset = 0x00 | ||
Because interrupts are only sampled at the end of an instruction by the Z80, each time the dma is interrupted one instruction of progress is made in the main program. | Because interrupts are only sampled at the end of an instruction by the Z80, each time the dma is interrupted one instruction of progress is made in the main program. | ||
Revision as of 20:14, 11 April 2026
| Next Register Number | $CC |
|---|---|
| Readable | Yes |
| Writable | Yes |
| Short Description | Interrupts that can override DMA |
bit 7 = NMI bit 1 = Line bit 0 = ULA
- Set bits indicate the corresponding interrupt will interrupt a dma operation when in hw im2 mode
Soft reset = 0x00
Because interrupts are only sampled at the end of an instruction by the Z80, each time the dma is interrupted one instruction of progress is made in the main program.