XADC Register: Difference between revisions
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updated to 78a6ee50 |
m Xalior moved page XADC register to XADC Register: match formal nextreg.txt name |
(No difference)
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Latest revision as of 12:48, 14 October 2025
| Number | TBRegisterNumber::$F8 |
|---|---|
| Readable | TBRegisterReadable::Yes |
| Writable | TBRegisterWritable::Yes |
| Short Description | ShortDesc::Issue 4 only |
bit 7 = 1 to write to XADC DRP port, 0 to read from XADC DRP port ** bits 6:0 = XADC DRP register address DADDR
- An XADC register read or write is initiated by writing to this register
- There must be at least six 28 MHz cycles after each r/w to this register
- ** Reads as 0