User contributions
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- 19:53, 30 December 2019 (diff | hist) . . (+133) . . m NEX file format
- 19:51, 30 December 2019 (diff | hist) . . (+32) . . NEX file format (V1.3 extensions proposal added)
- 19:50, 30 December 2019 (diff | hist) . . (+2,559) . . NEX file format
- 02:57, 30 December 2019 (diff | hist) . . (+122) . . NEX file format (Adding info about some NEX file having extra binary data appended to the "original" file)
- 02:11, 30 December 2019 (diff | hist) . . (+440) . . NEX file format (Adding info about current V1.3 header)
- 16:30, 29 December 2019 (diff | hist) . . (+311) . . DMA (fixing info based on the new experiments/evidence with Zilog DMA chip)
- 13:55, 25 December 2019 (diff | hist) . . (+174) . . DMA (fixing info based on the new experiments/evidence with Zilog DMA chip)
- 21:55, 18 December 2019 (diff | hist) . . (+35) . . DMA (extending info about Z80 interrupts in burst mode)
- 15:22, 18 December 2019 (diff | hist) . . (+2,621) . . DMA (writing down technical info collected in recent days)
- 19:10, 11 December 2019 (diff | hist) . . (+38) . . Peripheral 2 Register (summary enriched)
- 00:19, 10 December 2019 (diff | hist) . . (-132) . . Sprite port-mirror Attribute 3 (with INC) Register (refresh sprite info) (current)
- 00:15, 10 December 2019 (diff | hist) . . (-132) . . Sprite port-mirror Attribute 3 Register (refresh sprite info) (current)
- 21:56, 6 December 2019 (diff | hist) . . (+70) . . Sprite port-mirror Index Register (read register detail extended by info from Allen) (current)
- 00:26, 5 December 2019 (diff | hist) . . (+55) . . Machine Type Register (core 3.0.5 changes/refresh)
- 00:20, 5 December 2019 (diff | hist) . . (+264) . . CPU Speed Register (core 3.0.5 changes/refresh)
- 00:13, 5 December 2019 (diff | hist) . . (+52) . . Peripheral 4 Register (core 3.0.5 changes/refresh)
- 00:07, 5 December 2019 (diff | hist) . . (-493) . . Expansion Bus Control Register (core 3.0.5 changes/refresh) (current)
- 23:58, 4 December 2019 (diff | hist) . . (-373) . . Expansion Bus Enable Register (core 3.0.5 changes/refresh)
- 23:53, 4 December 2019 (diff | hist) . . (+996) . . m Expansion Bus Control Register (core 3.0.5 changes/refresh) (Tag: Removed redirect)
- 23:52, 4 December 2019 (diff | hist) . . (0) . . m Expansion Bus Enable Register (core 3.0.5 changes/refresh)
- 23:50, 4 December 2019 (diff | hist) . . (0) . . Expansion Bus Enable Register (core 3.0.5 changes/refresh)
- 23:48, 4 December 2019 (diff | hist) . . (0) . . m Expansion Bus Enable Register (Ped7g moved page Expansion Bus Control Register to Expansion Bus Enable Register: core 3.0.5 change/refresh)
- 23:48, 4 December 2019 (diff | hist) . . (+43) . . N Expansion Bus Control Register (Ped7g moved page Expansion Bus Control Register to Expansion Bus Enable Register: core 3.0.5 change/refresh) (Tag: New redirect)
- 23:46, 4 December 2019 (diff | hist) . . (+27) . . m Alternate ROM
- 23:45, 4 December 2019 (diff | hist) . . (+711) . . N Alternate ROM (core 3.0.5 changes/refresh)
- 21:14, 2 December 2019 (diff | hist) . . (+318) . . Memory Paging Control (core 3.0 changes/refresh)
- 20:51, 2 December 2019 (diff | hist) . . (+359) . . File Formats (SNA vs new NextZXOS info)
- 20:44, 2 December 2019 (diff | hist) . . (+28) . . Peripheral 3 Register (core 3.0 changes/refresh)
- 20:36, 2 December 2019 (diff | hist) . . (+333) . . Peripheral 3 Register (core 3.0 changes/refresh)
- 06:21, 1 December 2019 (diff | hist) . . (-7) . . Memory Paging Control (core 3.0 changes/refresh)
- 01:00, 1 December 2019 (diff | hist) . . (+96) . . Layer 2 RAM Shadow Page Register (core 3.0 changes/refresh) (current)
- 00:59, 1 December 2019 (diff | hist) . . (+96) . . Layer 2 RAM Page Register (core 3.0 changes/refresh)
- 04:20, 28 November 2019 (diff | hist) . . (-12) . . Memory map (core 3.0 changes/refresh) (current)
- 20:17, 27 November 2019 (diff | hist) . . (+378) . . Layer 2 Access Port (core 3.0 changes/refresh)
- 17:59, 27 November 2019 (diff | hist) . . (+56) . . m Layer 2 (core 3.0 changes/refresh)
- 17:35, 27 November 2019 (diff | hist) . . (+13) . . m Layer 2 (core 3.0 changes/refresh)
- 17:29, 27 November 2019 (diff | hist) . . (+1,286) . . Layer 2 (core 3.0 changes/refresh)
- 10:36, 16 November 2019 (diff | hist) . . (+115) . . Assemblers (updating sjasmplus description with new features from v1.14.3)
- 17:30, 12 November 2019 (diff | hist) . . (+1) . . m Pi I2S Clock Divide Register
- 17:30, 12 November 2019 (diff | hist) . . (+50) . . Pi I2S Clock Divide Register (fixing default value Hz result... (my math, argh))
- 12:39, 12 November 2019 (diff | hist) . . (+289) . . N Pi I2S Clock Divide Register (core 3.0 changes/refresh)
- 12:33, 12 November 2019 (diff | hist) . . (+723) . . N Pi I2S Audio Control Register (core 3.0 changes/refresh)
- 12:17, 12 November 2019 (diff | hist) . . (+675) . . N Pi Peripheral Enable Register (core 3.0 changes/refresh) (current)
- 11:54, 12 November 2019 (diff | hist) . . (+580) . . N Pi GPIO Register (core 3.0 changes/refresh) (current)
- 11:50, 12 November 2019 (diff | hist) . . (+86) . . m Pi GPIO Output Enable Register (core 3.0 changes/refresh) (current)
- 11:48, 12 November 2019 (diff | hist) . . (+450) . . N Pi GPIO Output Enable Register (core 3.0 changes/refresh)
- 11:42, 12 November 2019 (diff | hist) . . (+1,097) . . N Expansion Bus I/O Propagate Register (core 3.0 changes/refresh)
- 11:28, 12 November 2019 (diff | hist) . . (+860) . . N Expansion Bus Decoding b24-31 Register (core 3.0 changes/refresh)
- 11:26, 12 November 2019 (diff | hist) . . (+21) . . Internal Port Decoding b24-31 Register (core 3.0 changes/refresh)
- 11:22, 12 November 2019 (diff | hist) . . (+1,476) . . N Expansion Bus Decoding b16-23 Register (core 3.0 changes/refresh)
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