Property: Shortfx

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E
Extended Z80 instruction set#LD I, A +
I := A  +
Extended Z80 instruction set#DI +
IFF1:=0; IFF2:=0  +
Extended Z80 instruction set#EI +
IFF1:=1; IFF2:=1  +
Extended Z80 instruction set#RETN +
IFF1:=IFF2; PC:=SP*; SP+=2  +
Extended Z80 instruction set#ADD IXY, BC/DE/IXY/SP +
IXY+=rr  +
Extended Z80 instruction set#IM n +
Interrupt mode:=n  +
Extended Z80 instruction set#NOP +
PC+=1  +
Extended Z80 instruction set#JR nn +
PC+=nn  +
Extended Z80 instruction set#JP (HL) +
PC:=HL (not PC:=HL*)  +
Extended Z80 instruction set#JP (IXY) +
PC:=IXY (not PC:=IXY*)  +
Extended Z80 instruction set#JP (C) +
PC:=PC&$C000+IN(C)<<6  +
Extended Z80 instruction set#RET +
PC:=SP*; SP+=2  +
Extended Z80 instruction set#RETI +
PC:=SP*; SP+=2  +
Extended Z80 instruction set#JP nn +
PC:=nn  +
Extended Z80 instruction set#LD R, A +
R := A  +
Extended Z80 instruction set#LD SP, HL +
SP := HL  +
Extended Z80 instruction set#LD SP, IXY +
SP := IXY  +
Extended Z80 instruction set#CALL nn +
SP-=2; SP*:=PC; PC:=nn  +
Extended Z80 instruction set#PUSH nn +
SP-=2; SP*:=nn  +
Extended Z80 instruction set#PUSH BC/DE/HL/AF +
SP-=2; SP*:=rr  +
Extended Z80 instruction set#PUSH IXY +
SP-=2; SP*:=rr  +
Extended Z80 instruction set#CPDR +
do CPD while (!Z && BC>0)  +
Extended Z80 instruction set#CPIR +
do CPI while (!Z && BC>0)  +
Extended Z80 instruction set#INDR +
do IND while(B>0)  +
Extended Z80 instruction set#INIR +
do INI while(B>0)  +
Extended Z80 instruction set#LDDR +
do LDD while(BC>0)  +
Extended Z80 instruction set#LDDRX +
do LDDX while(BC>0)  +
Extended Z80 instruction set#LDIR +
do LDI while(BC>0)  +
Extended Z80 instruction set#LDIRX +
do LDIX while(BC>0)  +
Extended Z80 instruction set#OTDR +
do OUTD while (B>0)  +
Extended Z80 instruction set#OTIR +
do OUTI while (B>0)  +
Extended Z80 instruction set#LDPIRX +
do{t:=(HL&$FFF8+E&7)*; {if t!=A DE*:=t;} DE++; BC--}while(BC>0)  +
Extended Z80 instruction set#JR C/NC/Z/NZ, nn +
if cc PC+=nn  +
Extended Z80 instruction set#JP Z/NZ/NC/C/PO/PE/P/M, nn +
if cc PC:=nn  +
Extended Z80 instruction set#RET Z/NZ/C/NC/PO/PE/P/M +
if cc {PC:=SP*; SP+=2}  +
Extended Z80 instruction set#CALL Z/NZ/C/NC/PO/PE/P/M, nn +
if cc {SP-=2; SP*:=PC; PC:=nn}  +
Extended Z80 instruction set#DAA +
if(A&$0F>$09 or HF) A±=$06; if(A&$F0>$90 or CF) A±=$60 (± depends on NF)  +
Extended Z80 instruction set#PIXELDN +
if(HL&$0700!=$0700) HL+=256;<br> else if(HL&$e0!=$e0) HL:=HL&$F8FF+$20;<br> else HL:=HL&$F81F+$0800  +
Extended Z80 instruction set#IN (c) +
in(BC)?  +
Extended Z80 instruction set#OUT (n),A +
out(An,A)  +
Extended Z80 instruction set#OUT (c),0 +
out(BC,0)  +
Extended Z80 instruction set#OUTINB +
out(BC,HL*); HL++  +
Extended Z80 instruction set#OUT (c),r +
out(BC,r)  +
Extended Z80 instruction set#LD r, (IXY+d) +
r := (IXY+d)*  +
Extended Z80 instruction set#LD r, (HL) +
r := HL*  +
Extended Z80 instruction set#IN r, (c) +
r := in(BC)  +
Extended Z80 instruction set#LD r,n +
r := n  +
Extended Z80 instruction set#LD r, r' +
r := r'  +
Extended Z80 instruction set#INC r +
r++  +
Extended Z80 instruction set#DEC r +
r--  +
Extended Z80 instruction set#SL1 r +
r:=(r<<1)+1  +
Extended Z80 instruction set#RES b,r +
r:=r & (~(1<<b))  +
Extended Z80 instruction set#SET b,r +
r:=r OR (1<<b)  +
Extended Z80 instruction set#SLA r +
r:=r<<1  +
Extended Z80 instruction set#SRA r +
r:=r>>1 OR r[7]  +
Extended Z80 instruction set#SRL r +
r:=unsigned(r)>>1  +
Extended Z80 instruction set#BIT b,r +
r[b]==1?  +
Extended Z80 instruction set#LD BC/DE/SP/IXY, (nn) +
rr := (nn)*  +
Extended Z80 instruction set#LD BC/DE/HL/SP, nn +
rr := nn  +
Extended Z80 instruction set#LD IXY, nn +
rr := nn  +
Extended Z80 instruction set#LD (BC/DE), A +
rr* := A  +
Extended Z80 instruction set#INC BC/DE/HL/SP +
rr++  +
Extended Z80 instruction set#INC IXY +
rr++  +
Extended Z80 instruction set#ADD HL/DE/BC, nn +
rr+=nn  +
Extended Z80 instruction set#ADD HL/DE/BC, A +
rr+=unsigned A  +
Extended Z80 instruction set#DEC BC/DE/HL/SP +
rr--  +
Extended Z80 instruction set#DEC IXY +
rr--  +
Extended Z80 instruction set#POP BC/DE/HL +
rr:=SP*; SP+=2  +
Extended Z80 instruction set#POP AF +
rr:=SP*; SP+=2  +
Extended Z80 instruction set#POP IXY +
rr:=SP*; SP+=2  +
Extended Z80 instruction set#EX AF, AF' +
swap(AF,AF')  +
Extended Z80 instruction set#EXX +
swap(BC,BC');swap(DE,DE');swap(HL,HL')  +
Extended Z80 instruction set#EX DE, HL +
swap(DE,HL)  +
Extended Z80 instruction set#EX (SP), HL +
swap(SP*,HL)  +
Extended Z80 instruction set#EX (SP), IXY +
swap(SP*,IXY)  +
Extended Z80 instruction set#HALT +
waits for interrupt  +
Extended Z80 instruction set#RR r,(IX+d) +
x:=(IX+d)*[0]; (IX+d)*:=(IX+d)*>>1; (IX+d)*[7]:=CF; CF:=x; r=(IX+d)*  +
Extended Z80 instruction set#RRC r,(IX+d) +
x:=(IX+d)*[0]; (IX+d)*:=(IX+d)*>>1; (IX+d)*[7]:=x; CF:=x; r:=(IX+d)*  +
Extended Z80 instruction set#RL r,(IX+d) +
x:=(IX+d)*[7]; (IX+d)*:=(IX+d)*<<1; (IX+d)*[0]:=CF; CF:=x; r:=(IX+d)*  +
Extended Z80 instruction set#RLC r,(IX+d) +
x:=(IX+d)*[7]; (IX+d)*:=(IX+d)*<<1; (IX+d)*[0]:=x; CF:=x; r:=(IX+d)*  +
Extended Z80 instruction set#RR (IXY+d) +
x:=(IXY+d)*[0]; (IXY+d)*:=(IXY+d)*>>1; (IXY+d)*[7]:=CF; CF:=x  +
Extended Z80 instruction set#RRC (IXY+d) +
x:=(IXY+d)*[0]; (IXY+d)*:=(IXY+d)*>>1; (IXY+d)*[7]:=x; CF:=x  +
Extended Z80 instruction set#RL (IXY+d) +
x:=(IXY+d)*[7]; (IXY+d)*:=(IXY+d)*<<1; (IXY+d)*[0]:=CF; CF:=x  +
Extended Z80 instruction set#RLC (IXY+d) +
x:=(IXY+d)*[7]; (IXY+d)*:=(IXY+d)*<<1; (IXY+d)*[0]:=x; CF:=x  +
Extended Z80 instruction set#RRA +
x:=A[0]; A:=A>>1; A[7]:=CF; CF:=x  +
Extended Z80 instruction set#RRCA +
x:=A[0]; A:=A>>1; A[7]:=x; CF:=x  +
Extended Z80 instruction set#RLA +
x:=A[7]; A:=A<<1; A[0]:=CF; CF:=x  +
Extended Z80 instruction set#RLCA +
x:=A[7]; A:=A<<1; A[0]:=x; CF:=x  +
Extended Z80 instruction set#RR (HL) +
x:=HL*[0]; HL*:=HL*>>1; HL*[7]:=CF; CF:=x  +
Extended Z80 instruction set#RRC (HL) +
x:=HL*[0]; HL*:=HL*>>1; HL*[7]:=x; CF:=x  +
Extended Z80 instruction set#RL (HL) +
x:=HL*[7]; HL*:=HL*<<1; HL*[0]:=CF; CF:=x  +
Extended Z80 instruction set#RLC (HL) +
x:=HL*[7]; HL*:=HL*<<1; HL*[0]:=x; CF:=x  +
Extended Z80 instruction set#RR r +
x:=r[0]; r:=r>>1; r[7]:=CF; CF:=x  +
Extended Z80 instruction set#RRC r +
x:=r[0]; r:=r>>1; r[7]:=x; CF:=x  +
Extended Z80 instruction set#RL r +
x:=r[7]; r:=r<<1; r[0]:=CF; CF:=x  +
Extended Z80 instruction set#RLC r +
x:=r[7]; r:=r<<1; r[0]:=x; CF:=x  +
Extended Z80 instruction set#RLD +
x=HL*; HL*[0123]:=A[0123]; HL*[7654]:=x[0123]; A[0123]:=x[7654]  +
Extended Z80 instruction set#RRD +
x=HL*; HL*[7654]:=A[0123]; HL*[0123]:=x[7654]; A[0123]:=x[0123]  +
Extended Z80 instruction set#LDIX +
{if HL*!=A DE*:=HL*;} DE++; HL++; BC--  +
Extended Z80 instruction set#LDDX +
{if HL*!=A DE*:=HL*;} DE++; HL--; BC--  +
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