User contributions for Ped7g - SpecNext Wiki

Results for Ped7g talk block log uploads logs abuse log

A user with 693 edits. Account created on 14 April 2019.

Jump to: navigation, search

17:3817:38, 7 January 2020 diff hist +203 Display Control 1 Register adding info current
17:3717:37, 7 January 2020 diff hist +195 Memory Paging Control adding info
09:4509:45, 7 January 2020 diff hist +41 m NEX file format No edit summary

13:4813:48, 6 January 2020 diff hist +74 NEX file format V1.3 extensions proposal - probably final version of proposal, changes documented in text

23:0423:04, 4 January 2020 diff hist +1 m ULA Palette Control Register No edit summary
00:4500:45, 4 January 2020 diff hist +214 Layer 2 Control Register core 3.0.7 changes/refresh

17:0717:07, 3 January 2020 diff hist +36 NEX file format V1.3 extensions proposal - refined some details after testing NEXLOAD2 prototype
17:0517:05, 3 January 2020 diff hist −1 m NEX file format No edit summary
17:0417:04, 3 January 2020 diff hist +501 NEX file format V1.3 extensions proposal - refined some details after testing NEXLOAD2 prototype

17:2817:28, 2 January 2020 diff hist +85 m Layer 2 Control Register No edit summary
17:2617:26, 2 January 2020 diff hist +1,881 N Layer 2 Control Register core 3.0.7 changes/refresh

11:0511:05, 31 December 2019 diff hist +238 Datagear DMA Port add info
11:0011:00, 31 December 2019 diff hist +506 MB02 DMA Port core 3.0.7 changes/refresh
10:5510:55, 31 December 2019 diff hist +19 m Layer 2 Access Port No edit summary
10:5410:54, 31 December 2019 diff hist +1,469 Layer 2 Access Port core 3.0.7 changes/refresh
10:2010:20, 31 December 2019 diff hist +165 Plus 3 Memory Paging Control adding info
10:1610:16, 31 December 2019 diff hist +204 Next Memory Bank Select adding info
10:1410:14, 31 December 2019 diff hist +58 Memory Paging Control adding info
10:1010:10, 31 December 2019 diff hist +293 Video Modes core 3.0 changes/refresh
09:2909:29, 31 December 2019 diff hist +83 Timex Sinclair Video Mode Control fixing the description Enhanced ULA mechanics, and overall adding info
08:3708:37, 31 December 2019 diff hist +157 ULA Control Port adding info
08:2708:27, 31 December 2019 diff hist +187 Keyboard info about multi-row reading possible

18:5918:59, 30 December 2019 diff hist +317 NEX file format V1.3 extensions proposal: added copper code block
18:5318:53, 30 December 2019 diff hist +133 m NEX file format No edit summary
18:5118:51, 30 December 2019 diff hist +32 NEX file format V1.3 extensions proposal added
18:5018:50, 30 December 2019 diff hist +2,559 NEX file format No edit summary
01:5701:57, 30 December 2019 diff hist +122 NEX file format Adding info about some NEX file having extra binary data appended to the "original" file
01:1101:11, 30 December 2019 diff hist +440 NEX file format Adding info about current V1.3 header

15:3015:30, 29 December 2019 diff hist +311 DMA fixing info based on the new experiments/evidence with Zilog DMA chip

12:5512:55, 25 December 2019 diff hist +174 DMA fixing info based on the new experiments/evidence with Zilog DMA chip

20:5520:55, 18 December 2019 diff hist +35 DMA extending info about Z80 interrupts in burst mode
14:2214:22, 18 December 2019 diff hist +2,621 DMA writing down technical info collected in recent days

18:1018:10, 11 December 2019 diff hist +38 Peripheral 2 Setting Register summary enriched

23:1923:19, 9 December 2019 diff hist −132 Sprite Attribute 3 (with INC) Register refresh sprite info
23:1523:15, 9 December 2019 diff hist −132 Sprite Attribute 3 Register refresh sprite info

20:5620:56, 6 December 2019 diff hist +70 Sprite port-mirror Index Register read register detail extended by info from Allen current

23:2623:26, 4 December 2019 diff hist +55 Machine Type Register core 3.0.5 changes/refresh
23:2023:20, 4 December 2019 diff hist +264 CPU Speed Register core 3.0.5 changes/refresh
23:1323:13, 4 December 2019 diff hist +52 Peripheral 4 Setting Register core 3.0.5 changes/refresh
23:0723:07, 4 December 2019 diff hist −493 Expansion Bus Control Register core 3.0.5 changes/refresh
22:5822:58, 4 December 2019 diff hist −373 Expansion Bus Enable Register core 3.0.5 changes/refresh
22:5322:53, 4 December 2019 diff hist +996 m Expansion Bus Control Register core 3.0.5 changes/refresh Tag: Removed redirect
22:5222:52, 4 December 2019 diff hist 0 m Expansion Bus Enable Register core 3.0.5 changes/refresh
22:5022:50, 4 December 2019 diff hist 0 Expansion Bus Enable Register core 3.0.5 changes/refresh
22:4822:48, 4 December 2019 diff hist +43 N Expansion Bus Control Register Ped7g moved page Expansion Bus Control Register to Expansion Bus Enable Register: core 3.0.5 change/refresh Tag: New redirect
22:4822:48, 4 December 2019 diff hist 0 m Expansion Bus Enable Register Ped7g moved page Expansion Bus Control Register to Expansion Bus Enable Register: core 3.0.5 change/refresh
22:4622:46, 4 December 2019 diff hist +27 m Alternate ROM Register No edit summary
22:4522:45, 4 December 2019 diff hist +711 N Alternate ROM Register core 3.0.5 changes/refresh

20:1420:14, 2 December 2019 diff hist +318 Memory Paging Control core 3.0 changes/refresh
19:5119:51, 2 December 2019 diff hist +359 File Formats SNA vs new NextZXOS info

Retrieved from "http://wiki.specnext.dev/Special:Contributions/Ped7g"