Board feature control

This is a general list of ports and registers used to control features on the Spectrum Next board.

Note that these lists are automatically generated and not directly editable. To edit data on a port or register, visit its page. To add a new port, click here. To add a new register, click here.

Mapped Spectrum Ports

A note on partial decoding

Most Spectrum peripherals did not actually decode all 16 bits of the address bus; they checked only for certain bits, and would respond if those bit values were set correctly, regardless of the other bits. The "bitmask" column for each port shows the bits that are tested for by the device. Traditionally all "unused" bits are set to 1 to avoid conflicts with other devices, which is the basis of the given port numbers; but alternate port numbers may be used in some cases. However, beware of creating clashes: in particular any port which does not intend to access the ULA should have the LSB set, as the ULA checks only for a reset LSB.

It is not known if the Next's built-in devices will have this decoding restriction, but it seems a safe presumption that they will not except where needed by legacy code.

On the other hand, partial decoding can allow use of the multiple output opcodes such as OTIR, which normally places the loop counter on the top half of the address bus - thus making it useless except for devices which ignore this top half. This is the reason why some of the Next registers do ignore the top half of the port address.

	Number	Mask	Description
Keyboard	$**FE	%xxxx xxxx ---- ---0 where only one bit in x is 0	Series of specific ports that read keyboard key presses.
I2C clock	$103B	%0001 0000 0011 1011 ??	Sets and reads the I2C SCL line.
I2C data	$113B	%0001 0001 0011 1011 ??	Sets and reads the I2C SDA line
Layer 2 Access Port	$123B	%0001 0010 0011 1011 ??	Enables Layer 2 and controls paging of layer 2 screen into lower memory.
UART TX	$133B	%0001 0011 0011 1011	Sends byte to serial port. If read, tells if data in RX buffer
UART RX	$143B	%0001 0100 0011 1011	Reads data from serial port, write sets the baudrate
UART Control	$153B	%0001 0101 0011 1011	Configuration of UART interfaces
UART Frame	$163B	%0001 0110 0011 1011	UART Frame
CTC Channels	$183B	%0001 1XXX 0011 1011	CTC 8 channels 0x183b - 0x1f3b
Plus 3 Memory Paging Control	$1FFD	%0001 ---- ---- --0-	Controls ROM paging and special paging options from the +2a/+3.
TBBlue Register Select	$243B	%0010 0100 0011 1011	Selects active port for TBBlue/Next feature configuration.
TBBlue Register Access	$253B	%0010 0101 0011 1011	Reads and/or writes the selected TBBlue control register.
Sprite Status/Slot Select	$303B	%0011 0000 0011 1011 ??	Sets active sprite-attribute index and pattern-slot index, reads sprite status.
Memory Paging Control	$7FFD	%01-- ---- ---- --0-	Selects active RAM, ROM, and displayed screen.
AY Info	$BFF5	1011111111110101	AY information
Sound Chip Register Write	$BFFD	%10-- ---- ---- --0-	Writes to the selected register of the selected sound chip.
Next Memory Bank Select	$DFFD	%1101 1111 1111 1101	Provides additional bank select bits for extended memory.
DIVMMC	$E3		Divmmc control
Pentagon 1024 paging	$EFF7	1110111111110111	Paging in Pentagon 1024K mode
Kempston Mouse Buttons	$FADF	%---- ---0 --0- ----	Reads buttons on Kempston Mouse.
Kempston Mouse X	$FBDF	%---- -0-1 --0- ----	X coordinate of Kempston Mouse, 0-255.
Kempston Mouse Y	$FFDF	%---- -1-1 --0- ----	Y coordinate of Kempston Mouse, 0-192.
Turbo Sound Next Control	$FFFD	%11-- ---- ---- --0-	Controls stereo channels and selects active sound chip and sound chip channel.
MB02 DMA Port	$xx0B	---- ---- 0000 1011	Controls Z8410 DMA chip via MB02 standard.
Kempston Joystick	$xx1F	%---- ---- 0001 1111	Reads movement of joysticks using Kempston interface.
Kempston Joystick 2, Joystick I/O	$xx37		Kempston interface second joystick variant and controls joystick I/O.
Sprite Attribute Upload	$xx57	%---- ---- 0101 0111	Uploads sprite positions, visibility, colour type and effect flags.
Sprite Pattern Upload	$xx5B	%---- ---- 0101 1011 ??	Used to upload the pattern of the selected sprite.
Datagear DMA Port	$xx6B	---- ---- 0110 1011	Controls zxnDMA chip
SpecDrum DAC Output	$xxDF	%---- ---- --01 1111	Output to SpecDrum DAC.
ULA Control Port	$xxFE		Controls border color and base Spectrum audio settings.
Timex Sinclair Video Mode Control	$xxFF		Controls Timex Sinclair video modes and colours in hi-res mode.

Next/TBBlue Feature Control Registers

Specific features of the Next are controlled via these register numbers, accessed via TBBlue Register Select ($243B / 9275) and TBBlue Register Access ($253B / 9531), or via the NEXTREG opcode.

	Number	Readable	Writable	Description
Machine ID Register	$00	true	false	Identifies TBBlue board type. Should always be 10 (binary 0000 1010) on Next.
Core Version Register	$01	true	false	Identifies core (FPGA image) version.
Next Reset Register	$02	true	true	Identifies type of last reset. Can be written to force reset.
Machine Type Register	$03	true	true	Identifies timing and machine type.
Config Mapping Register	$04	false	true	In config mode, allows RAM to be mapped to ROM area.
Peripheral 1 Register	$05	true	true	Sets joystick mode, video frequency and Scandoubler.
Peripheral 2 Register	$06	true	true	Enables CPU Speed key, DivMMC, Multiface, Mouse and AY audio.
CPU Speed Register	$07	true	true	Sets CPU Speed, reads actual speed.
Peripheral 3 Register	$08	true	true	ABC/ACB Stereo, Internal Speaker, SpecDrum, Timex Video Modes, Turbo Sound Next, RAM contention and [un]lock 128k paging.
Peripheral 4 Register	$09	true	true	Sets scanlines, AY mono output, Sprite-id lockstep, reset DivMMC mapram and disable HDMI audio.
Peripheral 5 Register	$0A	true	true	Multiface type, Divmmc automap, Mouse buttons and DPI config
Joystick I/O Mode	$0B	true	true	Joystick port I/O control
Core Version Register (sub minor)	$0E	true	false	Identifies core (FPGA image) version (sub minor number).
Board ID	$0F	true	false	Spectrum next issue ID
Anti-brick Register	$10	true	true	Used within the Anti-brick system.
Video Timing Register	$11	true	true	Sets video output timing variant.
Layer 2 RAM Page Register	$12	true	true	Sets the bank number where Layer 2 video memory begins.
Layer 2 RAM Shadow Page Register	$13	true	true	Sets the bank number where the Layer 2 shadow screen begins.
Global Transparency Register	$14	true	true	Sets the "transparent" colour for Layer 2, ULA and LoRes pixel data.
Sprite and Layers System Register	$15	true	true	Enables/disables Sprites and Lores Layer, and chooses priority of sprites and Layer 2.
Layer 2 X Offset Register	$16	true	true	Sets the pixel offset used for drawing Layer 2 graphics on the screen.
Layer 2 Y Offset Register	$17	true	true	Sets the Y offset used when drawing Layer 2 graphics on the screen.
Clip Window Layer 2 Register	$18	true	true	Sets and reads clip-window for Layer 2.
Clip Window Sprites Register	$19	true	true	Sets and reads clip-window for Sprites
Clip Window ULA/LoRes Register	$1A	true	true	Sets and reads clip-window for ULA/LoRes layer.
Clip Window Tilemap Register	$1B	true	true	Sets and reads clip-window for Tilemap.
Clip Window Control Register	$1C	true	true	Controls (resets) the clip-window registers indices.
Active Video Line MSB Register	$1E	true	false	Holds the MSB (only, as bit 0) of the raster line currently being drawn.
Active Video Line LSB Register	$1F	true	false	Holds the eight LSBs of the raster line currently being drawn.
Generate Maskable Interrupt	$20	true	true	Trigger interrupt
Video Line Interrupt Control Register	$22	true	true	Controls the timing of raster interrupts and the ULA frame interrupt.
Video Line Interrupt Value Register	$23	true	true	Holds the eight LSBs of the line on which a raster interrupt should occur.
Reserved	$24	false	false	n/a
ULA X Offset Register	$26	true	true	Pixel X offset (0..255) to use when drawing ULA Layer.
ULA Y Offset Register	$27	true	true	Pixel Y offset (0..191) to use when drawing ULA Layer.
Keymap High Address Register	$28	true	true	PS/2 Keymap address MSB, read (pending) first byte of palette colour
Keymap Low Address Register	$29	false	true	PS/2 Keymap address LSB.
Keymap High Data Register	$2A	false	true	High data to PS/2 Keymap (MSB of data in bit 0)
Keymap Low Data Register	$2B	false	true	Low eight LSBs of PS/2 Keymap data.
DAC B (left) mirror Register	$2C	true	true	DAC B mirror, read current I2S left MSB
DAC A+D (mono) mirror Register	$2D	true	true	SpecDrum port 0xDF / DAC A+D mirror, read current I2S LSB
DAC C (right) mirror Register	$2E	true	true	DAC C mirror, read current I2S right MSB
Tilemap Offset X MSB Register	$2F	true	true	Sets the pixel offset (two high bits) used for drawing Tilemap graphics on the screen.
Tilemap Offset X LSB Register	$30	true	true	Sets the pixel offset (eight low bits) used for drawing Tilemap graphics on the screen.
Tilemap Offset Y Register	$31	true	true	Sets the pixel offset used for drawing Tilemap graphics on the screen.
LoRes X Offset Register	$32	true	true	Pixel X offset (0..255) to use when drawing LoRes Layer.
LoRes Y Offset Register	$33	true	true	Pixel Y offset (0..191) to use when drawing LoRes Layer.
Sprite port-mirror Index Register	$34	true	true	Selects sprite index 0..127 to be affected by writes to other Sprite ports (and mirrors).
Sprite port-mirror Attribute 0 Register	$35	false	true	Nextreg port-mirror to write directly into "byte 1" of Sprite Attribute Upload ($xx57 / 87).
Sprite port-mirror Attribute 1 Register	$36	false	true	Nextreg port-mirror to write directly into "byte 2" of Sprite Attribute Upload ($xx57 / 87).
Sprite port-mirror Attribute 2 Register	$37	false	true	Nextreg port-mirror to write directly into "byte 3" of Sprite Attribute Upload ($xx57 / 87).
Sprite port-mirror Attribute 3 Register	$38	false	true	Nextreg port-mirror to write directly into "byte 4" of Sprite Attribute Upload ($xx57 / 87).
Sprite port-mirror Attribute 4 Register	$39	false	true	Nextreg port-mirror to write directly into "byte 5" of Sprite Attribute Upload ($xx57 / 87).
Palette Index Register	$40	true	true	Chooses an palette element (index) to manipulate with
Palette Value Register	$41	true	true	Use to set/read 8-bit colours of the ULANext palette.
Enhanced ULA Ink Color Mask	$42	true	true	Specifies mask to extract ink colour from attribute cell value in ULANext mode.
Enhanced ULA Control Register	$43	true	true	Enables or disables Enhanced ULA interpretation of attribute values and toggles active palette.
Enhanced ULA Palette Extension	$44	true	true	Use to set 9-bit (2-byte) colours of the Enhanced ULA palette, or to read second byte of colour.
Transparency colour fallback Register	$4A	true	true	8-bit colour to be used when all layers contain transparent pixel.
Sprites Transparency Index Register	$4B	true	true	Index into sprite palette (of "transparent" colour).
Tilemap Transparency Index Register	$4C	true	true	Index into Tilemap palette (of "transparent" colour).
Memory management slot 0 bank	$50	true	true	Selects the 8k-bank stored in 8k-slot 0 (see Memory map).
Memory management slot 1 bank	$51	true	true	Selects the 8k-bank stored in 8k-slot 1 (see Memory map).
Memory management slot 2 bank	$52	true	true	Selects the 8k-bank stored in 8k-slot 2 (see Memory map).
Memory management slot 3 bank	$53	true	true	Selects the 8k-bank stored in 8k-slot 3 (see Memory map).
Memory management slot 4 bank	$54	true	true	Selects the 8k-bank stored in 8k-slot 4 (see Memory map).
Memory management slot 5 bank	$55	true	true	Selects the 8k-bank stored in 8k-slot 5 (see Memory map).
Memory management slot 6 bank	$56	true	true	Selects the 8k-bank stored in 8k-slot 6 (see Memory map).
Memory management slot 7 bank	$57	true	true	Selects the 8k-bank stored in 8k-slot 7 (see Memory map).
Copper Data	$60	false	true	Used to upload code to the Copper.
Copper Control Low Byte	$61	true	true	Holds low byte of Copper control bits.
Copper Control High Byte	$62	true	true	Holds high byte of Copper control flags.
Copper Data 16-bit Write Register	$63	false	true	Used to upload code to the Copper.
Vertical Video Line Offset Register	$64	true	true	Offset numbering of raster lines in copper/interrupt/active register
ULA Control Register	$68	true	true	Disable ULA, controls ULA mixing/blending, enable ULA+
Display Control 1 Register	$69	true	true	Layer2, ULA shadow, Timex $FF port
LoRes Control Register	$6A	true	true	LoRes Radastan mode
Tilemap Control Register	$6B	true	true	Controls Tilemap mode.
Default Tilemap Attribute Register	$6C	true	true	Default tile attribute for 8-bit only maps.
Tilemap Base Address Register	$6E	true	true	Base address of the 40x32 or 80x32 tile map (similar to text-mode of other computers).
Tile Definitions Base Address Register	$6F	true	true	Base address of the tiles' graphics.
Layer 2 Control Register	$70	true	true	Layer 2 resolution, palette offset
Layer 2 X Offset MSB Register	$71	true	true	Sets the pixel offset used for drawing Layer 2 graphics on the screen.
Sprite port-mirror Attribute 0 (with INC) Register	$75	false	true	Same as Sprite port-mirror Attribute 0 Register ($35) (write first byte of sprite-attributes), plus increments Sprite port-mirror Index Register ($34)
Sprite port-mirror Attribute 1 (with INC) Register	$76	false	true	Same as Sprite port-mirror Attribute 1 Register ($36) (write second byte of sprite-attributes), plus increments Sprite port-mirror Index Register ($34)
Sprite port-mirror Attribute 2 (with INC) Register	$77	false	true	Same as Sprite port-mirror Attribute 2 Register ($37) (write third byte of sprite-attributes), plus increments Sprite port-mirror Index Register ($34)
Sprite port-mirror Attribute 3 (with INC) Register	$78	false	true	Same as Sprite port-mirror Attribute 3 Register ($38) (write fourth byte of sprite-attributes), plus increments Sprite port-mirror Index Register ($34)
Sprite port-mirror Attribute 4 (with INC) Register	$79	false	true	The same as Sprite port-mirror Attribute 4 Register ($39) (write fifth byte of sprite-attributes), plus increments Sprite port-mirror Index Register ($34)
User Storage 0 Register	$7F	true	true	8-bit storage for user
Expansion Bus Enable Register	$80	true	true	Expansion bus enable/config
Expansion Bus Control Register	$81	true	true	Expansion bus controls
Internal Port Decoding b0-7 Register	$82	true	true	Enabling internal ports decoding
Internal Port Decoding b8-15 Register	$83	true	true	Enabling internal ports decoding
Internal Port Decoding b16-23 Register	$84	true	true	Enabling internal ports decoding
Internal Port Decoding b24-31 Register	$85	true	true	Enabling internal ports decoding
Expansion Bus Decoding b0-7 Register	$86	true	true	When expansion bus is enabled: Internal ports decoding mask
Expansion Bus Decoding b8-15 Register	$87	true	true	When expansion bus is enabled: Internal ports decoding mask
Expansion Bus Decoding b16-23 Register	$88	true	true	When expansion bus is enabled: Internal ports decoding mask
Expansion Bus Decoding b24-31 Register	$89	true	true	When expansion bus is enabled: Internal ports decoding mask
Expansion Bus I/O Propagate Register	$8A	true	true	Monitoring internal I/O or adding external keyboard
Alternate ROM	$8C	true	true	Enable alternate ROM or lock 48k ROM
Memory Mapping Register	$8E	true	true	Control classic 128K Spectrum memory mapping
Memory Mapping Mode	$8F	true	true	Select memory mapping mode
Pi GPIO Output Enable Register	$90-$93	true	true	Enables GPIO pins output
Pi GPIO Register	$98-$9B	true	true	GPIO pins mapped to Next Register
Pi Peripheral Enable Register	$A0	true	true	Enable Pi peripherals: UART, Pi hats, I2C, SPI
Pi I2S Audio Control Register	$A2	true	true	Pi I2S controls
Pi I2S Clock Divide Register	$A3	true	true	Pi I2S clock divide in master mode.
ESP WiFi GPIO Output Register	$A8	true	true	ESP WiFi GPIO Output
ESP WiFi GPIO Register	$A9	true	true	ESP WiFi GPIO Read/Write
Extended Keys 0 Register	$B0	true	false	Read Next keyboard compound keys separately
Extended Keys 1 Register	$B1	true	false	Read Next keyboard compound keys separately
DivMMC Trap Enable 1 Register	$B2	true	true	DivMMC trap configuration
Extended MD Pad Buttons	$B2	true	false	Reading additional buttons on MD pads
DivMMC Trap Enable 2 Register	$B4	true	true	DivMMC trap configuration
Divmmc Entry Points 0	$B8	true	true	DivMMC automap control
Divmmc Entry Points Valid 0	$B9	true	true	DivMMC entry point validity
Divmmc Entry Points Timing 0	$BA	true	true	Adjust delay of divmmc mapping
Divmmc Entry Points 1	$BB	true	true	DivMMC automap control
Interrupt Control	$C0	true	true
NMI Return Address LSB	$C2	true	true	LSB of NMI return address
NMI Return Address MSB	$C3	true	true	MSB of NMI return address
Interrupt Enable 0	$C4	true	true	Interrupt type enable control
Interrupt Enable 1	$C5	true	true	ctc interrupt enable control
Interrupt Enable 2	$C6	true	true	UART interrupt enable control
Interrupt Status 0	$C8	true	true	has interrupt occurred?
Interrupt Status 1	$C9	true	true	has ctc interrupt occurred?
Interrupt Status 2	$CA	true	true	Has UART interrupt happened?
DMA interrupt enable 0	$CC	true	true	Interrupts that can override DMA
DMA interrupt enable 1	$CD	true	true	CTC Interrupts that can override DMA
DMA interrupt enable 2	$CE	true	true	UART Interrupts that can override DMA
I/O Traps	$D8	true	true	experimental
I/O Trap Write	$D9	true	true	experimental
I/O Trap Cause	$DA	true	false	experimental
XDEV command	$F0	true	true	Issue 4 only
XADC register	$F8	true	true	Issue 4 only
XADC D0	$F9	true	true	Issue 4 only
XADC D1	$F9	true	true	Issue 4 only
Debug LED Control Register	$FF	false	true	Turns debug LEDs on and off on TBBlue implementations that have them.