DMA interrupt enable 0

Next Register Number	$CC
Readable	Yes
Writable	Yes
Short Description	Interrupts that can override DMA

 bit 7 = NMI
 bit 1 = Line
 bit 0 = ULA

• Set bits indicate the corresponding interrupt will interrupt a dma operation when in hw im2 mode

Soft reset = 0x00

Because interrupts are only sampled at the end of an instruction by the Z80, each time the dma is interrupted one instruction of progress is made in the main program.

A signal will force the dma to pause by giving up the bus and wait in a reacquire bus state while the cpu takes back control. There are some vagaries in the behaviour due to how the z80 works: the z80 does not check for an interrupt until the last T state of an instruction so it's possible the z80 executes one instruction before the isr is entered. This is mentioned here as a caution to programmers because normally you start the dma with an OUT and when the next instruction executes, the dma op has already finished. Not so with this arrangement as you could be executing one instruction following that OUT each time the dma is interrupted.

There is also a kind of priority inversion that can happen. If only a ctc channel can interrupt a dma operation, there could be higher priority interrupts pending. When the ctc channel interrupts the dma, the z80 services the higher priority interrupts first and then only returns control to the dma when the reti for the ctc channel isr executes. The dma is also prevented from reacquring the bus until after reti pops its return address to avoid stack overflow.