Board feature control

This is a general list of ports and registers used to control features of the Spectrum Next board with core 3.1.5. For latest version including new features check the gitlab repository of ZX Next FPGA core: ports.txt and nextreg.txt and changelog.md.

Note that these lists are automatically generated and not directly editable. To edit data on a port or register, visit its page. To add a new port, click here. To add a new register, click here.

Mapped Spectrum Ports

A note on partial decoding

Most Spectrum peripherals did not actually decode all 16 bits of the address bus; they checked only for certain bits, and would respond if those bit values were set correctly, regardless of the other bits. The "bitmask" column for each port shows the bits that are tested for by the device. Traditionally all "unused" bits are set to 1 to avoid conflicts with other devices, which is the basis of the given port numbers; but alternate port numbers may be used in some cases. However, beware of creating clashes: in particular any port which does not intend to access the ULA should have the LSB set, as the ULA checks only for a reset LSB.

It is not known if the Next's built-in devices will have this decoding restriction, but it seems a safe presumption that they will not except where needed by legacy code.

On the other hand, partial decoding can allow use of the multiple output opcodes such as OTIR, which normally places the loop counter on the top half of the address bus - thus making it useless except for devices which ignore this top half. This is the reason why some of the Next registers do ignore the top half of the port address.

	Hexadecimal	Decimal	Mask	Description
Keyboard	$**FE	254	%xxxx xxxx ---- ---0 where only one bit in x is 0	Series of specific ports that read keyboard key presses.
I2C clock	$103B	4155	%0001 0000 0011 1011 ??	Sets and reads the I2C SCL line.
I2C data	$113B	4411	%0001 0001 0011 1011 ??	Sets and reads the I2C SDA line
Layer 2 Access Port	$123B	4667	%0001 0010 0011 1011 ??	Enables Layer 2 and controls paging of layer 2 screen into lower memory.
UART TX	$133B	4923	%0001 0011 0011 1011	Sends byte to serial port. If read, tells if data in RX buffer
UART RX	$143B	5179	%0001 0100 0011 1011	Reads data from serial port, write sets the baudrate
UART Control	$153B	5435	%0001 0101 0011 1011	Configuration of UART interfaces
UART Frame	$163B	5691	%0001 0110 0011 1011	UART Frame
CTC Channels	$183B	6203	%0001 1XXX 0011 1011	CTC 8 channels 0x183b - 0x1f3b
Plus 3 Memory Paging Control	$1FFD	8189	%0001 ---- ---- --0-	Controls ROM paging and special paging options from the +2a/+3.
TBBlue Register Select	$243B	9275	%0010 0100 0011 1011	Selects active port for TBBlue/Next feature configuration.
TBBlue Register Access	$253B	9531	%0010 0101 0011 1011	Reads and/or writes the selected TBBlue control register.
Sprite Status/Slot Select	$303B	12347	%0011 0000 0011 1011 ??	Sets active sprite-attribute index and pattern-slot index, reads sprite status.
Memory Paging Control	$7FFD	32765	%01-- ---- ---- --0-	Selects active RAM, ROM, and displayed screen.
AY Info	$BFF5	49141	1011111111110101	AY information
Sound Chip Register Write	$BFFD	49149	%10-- ---- ---- --0-	Writes to the selected register of the selected sound chip.
Next Memory Bank Select	$DFFD	57341	%1101 1111 1111 1101	Provides additional bank select bits for extended memory.
DIVMMC	$E3	227		Divmmc control
Pentagon 1024 paging	$EFF7	61431	1110111111110111	Paging in Pentagon 1024K mode
Kempston Mouse Buttons	$FADF	64223	%---- ---0 --0- ----	Reads buttons on Kempston Mouse.
Kempston Mouse X	$FBDF	64479	%---- -0-1 --0- ----	X coordinate of Kempston Mouse, 0-255.
Kempston Mouse Y	$FFDF	65503	%---- -1-1 --0- ----	Y coordinate of Kempston Mouse, 0-192.
Turbo Sound Next Control	$FFFD	65533	%11-- ---- ---- --0-	Controls stereo channels and selects active sound chip and sound chip channel.
MB02 DMA Port	$xx0B	11	---- ---- 0000 1011	Controls Z8410 DMA chip via MB02 standard.
Kempston Joystick	$xx1F	31	%---- ---- 0001 1111	Reads movement of joysticks using Kempston interface.
Kempston Joystick 2, Joystick I/O	$xx37	55		Kempston interface second joystick variant and controls joystick I/O.
Sprite Attribute Upload	$xx57	87	%---- ---- 0101 0111	Uploads sprite positions, visibility, colour type and effect flags.
Sprite Pattern Upload	$xx5B	91	%---- ---- 0101 1011 ??	Used to upload the pattern of the selected sprite.
Datagear DMA Port	$xx6B	107	---- ---- 0110 1011	Controls zxnDMA chip
SpecDrum DAC Output	$xxDF	223	%---- ---- --01 1111	Output to SpecDrum DAC.
ULA Control Port	$xxFE	254		Controls border color and base Spectrum audio settings.
Timex Sinclair Video Mode Control	$xxFF	255		Controls Timex Sinclair video modes and colours in hi-res mode.

Next/TBBlue Feature Control Registers

Specific features of the Next are controlled via these register numbers, accessed via TBBlue Register Select ($243B / 9275) and TBBlue Register Access ($253B / 9531), or via the NEXTREG opcode.

	Number	Readable	Writable	Description
Machine ID Register	$00	Yes	No	Identifies TBBlue board type. Should always be 10 (binary 0000 1010) on Next.
Core Version Register	$01	Yes	No	Identifies core (FPGA image) version.
Next Reset Register	$02	Yes	Yes	Identifies type of last reset. Can be written to force reset.
Machine Type Register	$03	Yes	Yes	Identifies timing and machine type.
Config Mapping Register	$04	No	Yes	In config mode, allows RAM to be mapped to ROM area.
Peripheral 1 Register	$05	Yes	Yes	Sets joystick mode, video frequency and Scandoubler.
Peripheral 2 Register	$06	Yes	Yes	Enables CPU Speed key, DivMMC, Multiface, Mouse and AY audio.
CPU Speed Register	$07	Yes	Yes	Sets CPU Speed, reads actual speed.
Peripheral 3 Register	$08	Yes	Yes	ABC/ACB Stereo, Internal Speaker, SpecDrum, Timex Video Modes, Turbo Sound Next, RAM contention and [un]lock 128k paging.
Peripheral 4 Register	$09	Yes	Yes	Sets scanlines, AY mono output, Sprite-id lockstep, reset DivMMC mapram and disable HDMI audio.
Peripheral 5 Register	$0A	Yes	Yes	Multiface type, Divmmc automap, Mouse buttons and DPI config
Joystick I/O Mode	$0B	Yes	Yes	Joystick port I/O control
Core Version Register (sub minor)	$0E	Yes	No	Identifies core (FPGA image) version (sub minor number).
Board ID	$0F	Yes	No	Spectrum next issue ID
Anti-brick Register	$10	Yes	Yes	Used within the Anti-brick system.
Video Timing Register	$11	Yes	Yes	Sets video output timing variant.
Layer 2 RAM Page Register	$12	Yes	Yes	Sets the bank number where Layer 2 video memory begins.
Layer 2 RAM Shadow Page Register	$13	Yes	Yes	Sets the bank number where the Layer 2 shadow screen begins.
Global Transparency Register	$14	Yes	Yes	Sets the "transparent" colour for Layer 2, ULA and LoRes pixel data.
Sprite and Layers System Register	$15	Yes	Yes	Enables/disables Sprites and Lores Layer, and chooses priority of sprites and Layer 2.
Layer 2 X Offset Register	$16	Yes	Yes	Sets the pixel offset used for drawing Layer 2 graphics on the screen.
Layer 2 Y Offset Register	$17	Yes	Yes	Sets the Y offset used when drawing Layer 2 graphics on the screen.
Clip Window Layer 2 Register	$18	Yes	Yes	Sets and reads clip-window for Layer 2.
Clip Window Sprites Register	$19	Yes	Yes	Sets and reads clip-window for Sprites
Clip Window ULA/LoRes Register	$1A	Yes	Yes	Sets and reads clip-window for ULA/LoRes layer.
Clip Window Tilemap Register	$1B	Yes	Yes	Sets and reads clip-window for Tilemap.
Clip Window Control Register	$1C	Yes	Yes	Controls (resets) the clip-window registers indices.
Active Video Line MSB Register	$1E	Yes	No	Holds the MSB (only, as bit 0) of the raster line currently being drawn.
Active Video Line LSB Register	$1F	Yes	No	Holds the eight LSBs of the raster line currently being drawn.
Generate Maskable Interrupt	$20	Yes	Yes	Trigger interrupt
Video Line Interrupt Control Register	$22	Yes	Yes	Controls the timing of raster interrupts and the ULA frame interrupt.
Video Line Interrupt Value Register	$23	Yes	Yes	Holds the eight LSBs of the line on which a raster interrupt should occur.
Reserved	$24	No	No	n/a
ULA X Offset Register	$26	Yes	Yes	Pixel X offset (0..255) to use when drawing ULA Layer.
ULA Y Offset Register	$27	Yes	Yes	Pixel Y offset (0..191) to use when drawing ULA Layer.
Keymap High Address Register	$28	Yes	Yes	PS/2 Keymap address MSB, read (pending) first byte of palette colour
Keymap Low Address Register	$29	No	Yes	PS/2 Keymap address LSB.
Keymap High Data Register	$2A	No	Yes	High data to PS/2 Keymap (MSB of data in bit 0)
Keymap Low Data Register	$2B	No	Yes	Low eight LSBs of PS/2 Keymap data.
DAC B (left) mirror Register	$2C	Yes	Yes	DAC B mirror, read current I2S left MSB
DAC A+D (mono) mirror Register	$2D	Yes	Yes	SpecDrum port 0xDF / DAC A+D mirror, read current I2S LSB
DAC C (right) mirror Register	$2E	Yes	Yes	DAC C mirror, read current I2S right MSB
Tilemap Offset X MSB Register	$2F	Yes	Yes	Sets the pixel offset (two high bits) used for drawing Tilemap graphics on the screen.
Tilemap Offset X LSB Register	$30	Yes	Yes	Sets the pixel offset (eight low bits) used for drawing Tilemap graphics on the screen.
Tilemap Offset Y Register	$31	Yes	Yes	Sets the pixel offset used for drawing Tilemap graphics on the screen.
LoRes X Offset Register	$32	Yes	Yes	Pixel X offset (0..255) to use when drawing LoRes Layer.
LoRes Y Offset Register	$33	Yes	Yes	Pixel Y offset (0..191) to use when drawing LoRes Layer.
Sprite port-mirror Index Register	$34	Yes	Yes	Selects sprite index 0..127 to be affected by writes to other Sprite ports (and mirrors).
Sprite port-mirror Attribute 0 Register	$35	No	Yes	Nextreg port-mirror to write directly into "byte 1" of Sprite Attribute Upload ($xx57 / 87).
Sprite port-mirror Attribute 1 Register	$36	No	Yes	Nextreg port-mirror to write directly into "byte 2" of Sprite Attribute Upload ($xx57 / 87).
Sprite port-mirror Attribute 2 Register	$37	No	Yes	Nextreg port-mirror to write directly into "byte 3" of Sprite Attribute Upload ($xx57 / 87).
Sprite port-mirror Attribute 3 Register	$38	No	Yes	Nextreg port-mirror to write directly into "byte 4" of Sprite Attribute Upload ($xx57 / 87).
Sprite port-mirror Attribute 4 Register	$39	No	Yes	Nextreg port-mirror to write directly into "byte 5" of Sprite Attribute Upload ($xx57 / 87).
Palette Index Register	$40	Yes	Yes	Chooses an palette element (index) to manipulate with
Palette Value Register	$41	Yes	Yes	Use to set/read 8-bit colours of the ULANext palette.
Enhanced ULA Ink Color Mask	$42	Yes	Yes	Specifies mask to extract ink colour from attribute cell value in ULANext mode.
Enhanced ULA Control Register	$43	Yes	Yes	Enables or disables Enhanced ULA interpretation of attribute values and toggles active palette.
Enhanced ULA Palette Extension	$44	Yes	Yes	Use to set 9-bit (2-byte) colours of the Enhanced ULA palette, or to read second byte of colour.
Transparency colour fallback Register	$4A	Yes	Yes	8-bit colour to be used when all layers contain transparent pixel.
Sprites Transparency Index Register	$4B	Yes	Yes	Index into sprite palette (of "transparent" colour).
Tilemap Transparency Index Register	$4C	Yes	Yes	Index into Tilemap palette (of "transparent" colour).
Memory management slot 0 bank	$50	Yes	Yes	Selects the 8k-bank stored in 8k-slot 0 (see Memory map).
Memory management slot 1 bank	$51	Yes	Yes	Selects the 8k-bank stored in 8k-slot 1 (see Memory map).
Memory management slot 2 bank	$52	Yes	Yes	Selects the 8k-bank stored in 8k-slot 2 (see Memory map).
Memory management slot 3 bank	$53	Yes	Yes	Selects the 8k-bank stored in 8k-slot 3 (see Memory map).
Memory management slot 4 bank	$54	Yes	Yes	Selects the 8k-bank stored in 8k-slot 4 (see Memory map).
Memory management slot 5 bank	$55	Yes	Yes	Selects the 8k-bank stored in 8k-slot 5 (see Memory map).
Memory management slot 6 bank	$56	Yes	Yes	Selects the 8k-bank stored in 8k-slot 6 (see Memory map).
Memory management slot 7 bank	$57	Yes	Yes	Selects the 8k-bank stored in 8k-slot 7 (see Memory map).
Copper Data	$60	No	Yes	Used to upload code to the Copper.
Copper Control Low Byte	$61	Yes	Yes	Holds low byte of Copper control bits.
Copper Control High Byte	$62	Yes	Yes	Holds high byte of Copper control flags.
Copper Data 16-bit Write Register	$63	No	Yes	Used to upload code to the Copper.
Vertical Video Line Offset Register	$64	Yes	Yes	Offset numbering of raster lines in copper/interrupt/active register
ULA Control Register	$68	Yes	Yes	Disable ULA, controls ULA mixing/blending, enable ULA+
Display Control 1 Register	$69	Yes	Yes	Layer2, ULA shadow, Timex $FF port
LoRes Control Register	$6A	Yes	Yes	LoRes Radastan mode
Tilemap Control Register	$6B	Yes	Yes	Controls Tilemap mode.
Default Tilemap Attribute Register	$6C	Yes	Yes	Default tile attribute for 8-bit only maps.
Tilemap Base Address Register	$6E	Yes	Yes	Base address of the 40x32 or 80x32 tile map (similar to text-mode of other computers).
Tile Definitions Base Address Register	$6F	Yes	Yes	Base address of the tiles' graphics.
Layer 2 Control Register	$70	Yes	Yes	Layer 2 resolution, palette offset
Layer 2 X Offset MSB Register	$71	Yes	Yes	Sets the pixel offset used for drawing Layer 2 graphics on the screen.
Sprite port-mirror Attribute 0 (with INC) Register	$75	No	Yes	Same as Sprite port-mirror Attribute 0 Register ($35) (write first byte of sprite-attributes), plus increments Sprite port-mirror Index Register ($34)
Sprite port-mirror Attribute 1 (with INC) Register	$76	No	Yes	Same as Sprite port-mirror Attribute 1 Register ($36) (write second byte of sprite-attributes), plus increments Sprite port-mirror Index Register ($34)
Sprite port-mirror Attribute 2 (with INC) Register	$77	No	Yes	Same as Sprite port-mirror Attribute 2 Register ($37) (write third byte of sprite-attributes), plus increments Sprite port-mirror Index Register ($34)
Sprite port-mirror Attribute 3 (with INC) Register	$78	No	Yes	Same as Sprite port-mirror Attribute 3 Register ($38) (write fourth byte of sprite-attributes), plus increments Sprite port-mirror Index Register ($34)
Sprite port-mirror Attribute 4 (with INC) Register	$79	No	Yes	The same as Sprite port-mirror Attribute 4 Register ($39) (write fifth byte of sprite-attributes), plus increments Sprite port-mirror Index Register ($34)
User Storage 0 Register	$7F	Yes	Yes	8-bit storage for user
Expansion Bus Enable Register	$80	Yes	Yes	Expansion bus enable/config
Expansion Bus Control Register	$81	Yes	Yes	Expansion bus controls
Internal Port Decoding b0-7 Register	$82	Yes	Yes	Enabling internal ports decoding
Internal Port Decoding b8-15 Register	$83	Yes	Yes	Enabling internal ports decoding
Internal Port Decoding b16-23 Register	$84	Yes	Yes	Enabling internal ports decoding
Internal Port Decoding b24-31 Register	$85	Yes	Yes	Enabling internal ports decoding
Expansion Bus Decoding b0-7 Register	$86	Yes	Yes	When expansion bus is enabled: Internal ports decoding mask
Expansion Bus Decoding b8-15 Register	$87	Yes	Yes	When expansion bus is enabled: Internal ports decoding mask
Expansion Bus Decoding b16-23 Register	$88	Yes	Yes	When expansion bus is enabled: Internal ports decoding mask
Expansion Bus Decoding b24-31 Register	$89	Yes	Yes	When expansion bus is enabled: Internal ports decoding mask
Expansion Bus I/O Propagate Register	$8A	Yes	Yes	Monitoring internal I/O or adding external keyboard
Alternate ROM	$8C	Yes	Yes	Enable alternate ROM or lock 48k ROM
Memory Mapping Register	$8E	Yes	Yes	Control classic 128K Spectrum memory mapping
Memory Mapping Mode	$8F	Yes	Yes	Select memory mapping mode
Pi GPIO Output Enable Register	$90-$93	Yes	Yes	Enables GPIO pins output
Pi GPIO Register	$98-$9B	Yes	Yes	GPIO pins mapped to Next Register
Pi Peripheral Enable Register	$A0	Yes	Yes	Enable Pi peripherals: UART, Pi hats, I2C, SPI
Pi I2S Audio Control Register	$A2	Yes	Yes	Pi I2S controls
Pi I2S Clock Divide Register	$A3	Yes	Yes	Pi I2S clock divide in master mode.
ESP WiFi GPIO Output Register	$A8	Yes	Yes	ESP WiFi GPIO Output
ESP WiFi GPIO Register	$A9	Yes	Yes	ESP WiFi GPIO Read/Write
Extended Keys 0 Register	$B0	Yes	No	Read Next keyboard compound keys separately
Extended Keys 1 Register	$B1	Yes	No	Read Next keyboard compound keys separately
DivMMC Trap Enable 1 Register	$B2	Yes	Yes	DivMMC trap configuration
Extended MD Pad Buttons	$B2	Yes	No	Reading additional buttons on MD pads
DivMMC Trap Enable 2 Register	$B4	Yes	Yes	DivMMC trap configuration
Divmmc Entry Points 0	$B8	Yes	Yes	DivMMC automap control
Divmmc Entry Points Valid 0	$B9	Yes	Yes	DivMMC entry point validity
Divmmc Entry Points Timing 0	$BA	Yes	Yes	Adjust delay of divmmc mapping
Divmmc Entry Points 1	$BB	Yes	Yes	DivMMC automap control
Interrupt Control	$C0	Yes	Yes
NMI Return Address LSB	$C2	Yes	Yes	LSB of NMI return address
NMI Return Address MSB	$C3	Yes	Yes	MSB of NMI return address
Interrupt Enable 0	$C4	Yes	Yes	Interrupt type enable control
Interrupt Enable 1	$C5	Yes	Yes	ctc interrupt enable control
Interrupt Enable 2	$C6	Yes	Yes	UART interrupt enable control
Interrupt Status 0	$C8	Yes	Yes	has interrupt occurred?
Interrupt Status 1	$C9	Yes	Yes	has ctc interrupt occurred?
Interrupt Status 2	$CA	Yes	Yes	Has UART interrupt happened?
DMA interrupt enable 0	$CC	Yes	Yes	Interrupts that can override DMA
DMA interrupt enable 1	$CD	Yes	Yes	CTC Interrupts that can override DMA
DMA interrupt enable 2	$CE	Yes	Yes	UART Interrupts that can override DMA
I/O Traps	$D8	Yes	Yes	experimental
I/O Trap Write	$D9	Yes	Yes	experimental
I/O Trap Cause	$DA	Yes	No	experimental
XDEV command	$F0	Yes	Yes	Issue 4 only
XADC register	$F8	Yes	Yes	Issue 4 only
XADC D0	$F9	Yes	Yes	Issue 4 only
XADC D1	$F9	Yes	Yes	Issue 4 only
Debug LED Control Register	$FF	No	Yes	Turns debug LEDs on and off on TBBlue implementations that have them.