Difference between revisions of "XADC D1"
From SpecNext official Wiki
(updated to 78a6ee50) |
(Correct incorrect register number to correct : Number=$FA as per https://gitlab.com/SpectrumNext/ZX_Spectrum_Next_FPGA/-/blob/master/cores/zxnext/nextreg.txt) |
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| Line 1: | Line 1: | ||
{{NextRegister | {{NextRegister | ||
| − | |Number=$ | + | |Number=$FA |
|Readable=Yes | |Readable=Yes | ||
|Writable=Yes | |Writable=Yes | ||
Latest revision as of 00:33, 7 April 2025
| Number | $FA |
|---|---|
| Readable | Yes |
| Writable | Yes |
| Short Description | Issue 4 only |
bits 7:0 = MSB data connected to XADC DRP data bus D15:8
DRP reads store result here, DRP writes take value from here