Difference between revisions of "Next Reset Register"
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Read: | Read: | ||
| − | bit 7 = | + | bit 7 = 1 if the reset signal to the expansion bus and esp is asserted |
| − | bits 6:2 = | + | bits 6:5 = Reserved |
| − | bit 1 = | + | bit 4 = 1 if multiface nmi was generated by an i/o trap (experimental, see nextreg 0xda) |
| − | bit 0 = | + | bit 3 = 1 if multiface nmi was generated by this nextreg |
| + | bit 2 = 1 if divmmc nmi was generated by this nextreg | ||
| + | bit 1 = 1 if the last reset was a hard reset | ||
| + | bit 0 = 1 if the last reset was a soft reset | ||
* Only one of bits 1:0 will be set | * Only one of bits 1:0 will be set | ||
Write: | Write: | ||
| − | + | bits 6:5 = Reserved must be zero | |
| − | bits 6: | + | bit 4 = Clear i/o trap (write zero to clear) (experimental) ** |
| − | bit 3 = | + | bit 3 = Generate multiface nmi (write zero to clear) ** |
| − | bit 2 = | + | bit 2 = Generate divmmc nmi (write zero to clear) ** |
| − | bit 1 = Generate a hard reset (reboot) | + | bit 1 = Generate a hard reset (reboot) * |
| − | bit 0 = Generate a soft reset | + | bit 0 = Generate a soft reset * |
* Hard reset has precedence | * Hard reset has precedence | ||
| + | ** These signals are ignored if the multiface, divmmc, dma or external nmi master is active | ||
| + | ** Copper cannot clear these bits | ||
| + | ** An i/o trap could occur at the same time as mf / divmmc cause; always check this bit in nmi isr if important | ||
| + | |||
| + | |||
| + | A useful NEXTREG 2, 8 will trigger the NextZXOS debugger status page, a hardware breakpoint. | ||
Latest revision as of 10:46, 3 November 2024
| Number | $02 |
|---|---|
| Readable | Yes |
| Writable | Yes |
| Short Description | Identifies type of last reset. Can be written to force reset. |
Read:
bit 7 = 1 if the reset signal to the expansion bus and esp is asserted bits 6:5 = Reserved bit 4 = 1 if multiface nmi was generated by an i/o trap (experimental, see nextreg 0xda) bit 3 = 1 if multiface nmi was generated by this nextreg bit 2 = 1 if divmmc nmi was generated by this nextreg bit 1 = 1 if the last reset was a hard reset bit 0 = 1 if the last reset was a soft reset * Only one of bits 1:0 will be set
Write:
bits 6:5 = Reserved must be zero bit 4 = Clear i/o trap (write zero to clear) (experimental) ** bit 3 = Generate multiface nmi (write zero to clear) ** bit 2 = Generate divmmc nmi (write zero to clear) ** bit 1 = Generate a hard reset (reboot) * bit 0 = Generate a soft reset * * Hard reset has precedence ** These signals are ignored if the multiface, divmmc, dma or external nmi master is active ** Copper cannot clear these bits ** An i/o trap could occur at the same time as mf / divmmc cause; always check this bit in nmi isr if important
A useful NEXTREG 2, 8 will trigger the NextZXOS debugger status page, a hardware breakpoint.