Video Line Interrupt Control Register: Difference between revisions
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m Ped7g moved page Raster Interrupt Control Register to Video Line Interrupt Control Register: sync with "nextreg.txt" terminology |
updated to 78a6ee50 |
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| 6-3 || Reserved, must be 0 | | 6-3 || Reserved, must be 0 | ||
|- | |- | ||
| 2 || If 1 disables original ULA interrupt (Reset to 0 after a reset) | | 2 || If 1 disables original ULA interrupt (Reset to 0 after a reset) ** | ||
|- | |- | ||
| 1 || If 1 enables Line Interrupt (Reset to 0 after a reset) | | 1 || If 1 enables Line Interrupt (Reset to 0 after a reset) ** | ||
|- | |- | ||
| 0 || MSB of Line Interrupt line value (Reset to 0 after a reset) | | 0 || MSB of Line Interrupt line value (Reset to 0 after a reset) | ||
|} | |} | ||
** Aliases of interrupt enable bits in nextreg 0xC4. | |||
The line interrupt value uses coordinate system of [https://gitlab.com/thesmog358/tbblue/blob/master/docs/extra-hw/copper/COPPER-v0.1c.TXT Copper coprocessor], i.e. line 0 is the first line of pixels. But the line-interrupt happens already when the previous line's pixel area is finished (i.e. the raster-line counter still reads "previous line" and not the one programmed for interrupt). The INT signal is raised while display beam horizontal position is between 256-319 standard pixels, precise timing of interrupt handler execution then depends on how-quickly/if the Z80 will process the INT signal. | The line interrupt value uses coordinate system of [https://gitlab.com/thesmog358/tbblue/blob/master/docs/extra-hw/copper/COPPER-v0.1c.TXT Copper coprocessor], i.e. line 0 is the first line of pixels. But the line-interrupt happens already when the previous line's pixel area is finished (i.e. the raster-line counter still reads "previous line" and not the one programmed for interrupt). The INT signal is raised while display beam horizontal position is between 256-319 standard pixels, precise timing of interrupt handler execution then depends on how-quickly/if the Z80 will process the INT signal. | ||
The LSB part of desired interrupt line is in {{NextRegNo|$23}}. | The LSB part of desired interrupt line is in {{NextRegNo|$23}}. | ||
Since core 3.1.5 the numbering of lines can be offset by {{NextRegNo|$64}}. | |||
Latest revision as of 11:31, 3 November 2024
| Number | TBRegisterNumber::$22 |
|---|---|
| Readable | TBRegisterReadable::Yes |
| Writable | TBRegisterWritable::Yes |
| Short Description | ShortDesc::Controls the timing of raster interrupts and the ULA frame interrupt. |
| Bit | Function |
|---|---|
| 7 | (R) INT signal (even when Z80N has interrupts disabled) (1 = interrupt is requested)
(W) Reserved, must be 0 |
| 6-3 | Reserved, must be 0 |
| 2 | If 1 disables original ULA interrupt (Reset to 0 after a reset) ** |
| 1 | If 1 enables Line Interrupt (Reset to 0 after a reset) ** |
| 0 | MSB of Line Interrupt line value (Reset to 0 after a reset) |
** Aliases of interrupt enable bits in nextreg 0xC4.
The line interrupt value uses coordinate system of Copper coprocessor, i.e. line 0 is the first line of pixels. But the line-interrupt happens already when the previous line's pixel area is finished (i.e. the raster-line counter still reads "previous line" and not the one programmed for interrupt). The INT signal is raised while display beam horizontal position is between 256-319 standard pixels, precise timing of interrupt handler execution then depends on how-quickly/if the Z80 will process the INT signal.
The LSB part of desired interrupt line is in {{#ask: TBRegisterNumber::$23 }} ($23).
Since core 3.1.5 the numbering of lines can be offset by {{#ask: TBRegisterNumber::$64 }} ($64).