Difference between revisions of "Expansion Bus Control Register"
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(core 3.0.5 changes/refresh) |
(updated to 78a6ee50) |
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| 7 || 1 if ROMCS is being asserted on the expansion bus (Read only, write 0) | | 7 || 1 if ROMCS is being asserted on the expansion bus (Read only, write 0) | ||
| + | |- | ||
| + | | 6 || 1 to allow peripherals to override the ULA on some even port reads (rotronics wafadrive) | ||
| + | |- | ||
| + | | 5 || 1 to disable expansion bus nmi debounce (opus discovery) | ||
|- | |- | ||
| 4 || 1 to propagate the max CPU clock at all times including when the expansion bus is off | | 4 || 1 to propagate the max CPU clock at all times including when the expansion bus is off | ||
Latest revision as of 11:45, 3 November 2024
| Number | $81 |
|---|---|
| Readable | Yes |
| Writable | Yes |
| Short Description | Expansion bus controls |
| Bit | Description |
|---|---|
| 7 | 1 if ROMCS is being asserted on the expansion bus (Read only, write 0) |
| 6 | 1 to allow peripherals to override the ULA on some even port reads (rotronics wafadrive) |
| 5 | 1 to disable expansion bus nmi debounce (opus discovery) |
| 4 | 1 to propagate the max CPU clock at all times including when the expansion bus is off |
| 1-0 | max CPU speed when the expansion bus is on (currently fixed at 00 = 3.5MHz) |
Set to 0 upon hard reset.
(new register since core 3.0.5)
(note: Next registers with number higher than $7F are inaccessible from Copper code)