Generate Maskable Interrupt Register: Difference between revisions
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updated to 78a6ee50 |
m Xalior moved page Generate Maskable Interrupt to Generate Maskable Interrupt Register: match formal nextreg.txt name |
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Latest revision as of 17:37, 13 October 2025
| Number | TBRegisterNumber::$20 |
|---|---|
| Readable | TBRegisterReadable::Yes |
| Writable | TBRegisterWritable::Yes |
| Short Description | ShortDesc::Trigger interrupt |
bit 7 = line bit 6 = ula bits 5:4 = reserved bits 3:0 = ctc 3:0
- Set bits on R indicate whether an interrupt occurred or is pending (alias of bits in NR 0xC8 - 0xCA)
- Set bits on W always generate a maskable interrupt ignoring enables (NR 0xC4 - 0xC6)