Peripheral 2 Setting Register: Difference between revisions
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updated to 78a6ee50 |
m Xalior moved page Peripheral 2 Register to Peripheral 2 Setting Register: match formal nextreg.txt name |
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(No difference)
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Latest revision as of 14:47, 13 October 2025
| Number | TBRegisterNumber::$06 |
|---|---|
| Readable | TBRegisterReadable::Yes |
| Writable | TBRegisterWritable::Yes |
| Short Description | [[ShortDesc::Enables CPU Speed key, DivMMC, Multiface, Mouse and AY audio.]] |
| Bit | Function |
|---|---|
| 7 | Enable CPU speed mode key "F8", and F5/F6 expansion bus hotkeys 0 = disabled (1 after Soft-reset) |
| 6 | core3.1.2: Divert BEEP-only to internal speaker (hard reset = 0)
|
| 5 | Enable "F3" key (50/60 Hz switch) (1 after Soft-reset) (was "Enable Lightpen" in core 2.0) |
| 4 | Enable DivMMC NMI by DRIVE button (0 after Hard-reset) |
| 3 | Enable multiface NMI by M1 button (hard reset = 0) |
| 2 | PS/2 mode (primary device: 0 = keyboard, 1 = mouse), exchanges the keyboard/mouse pins on the PS/2 connector (writeable only in config mode) |
| 1-0 | Audio chip mode (%00 = YM, %01 = AY, %10 = ZXN-8950, %11 = Hold all AY in reset)
(core 3.0) %11 hold all AY in reset |
The bit 7 doesn't prevent SW from setting up different CPU speed by writing into {{#ask: TBRegisterNumber::$07 }} ($07), it is used only to enable/disable the "F8" key toggle, similarly bit 5 enables "F3" key.
NEW in core 3.0:
bit 5 = enable F3 (50/60 Hz) bit 2 ps2mode only modifiable in config mode chip mode = 11 resets all AY
NEW in core 3.1.2:
bit 6 = BEEP-only into internal speaker (DMA does use two I/O ports now)