Difference between revisions of "GPIO Socket (J15)"

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m (FPGA page link)
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* I2C serial protocol
 
* I2C serial protocol
 
* UART
 
* UART
* Spare pins on the FPGA
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* Spare pins on the [[FPGA]]
 
* 5v, 3.3v and GND
 
* 5v, 3.3v and GND
  

Revision as of 13:11, 4 July 2019

The GPIO socket, marked J15 on the circuit board, allows access to several different power and data lines:

  • I2C serial protocol
  • UART
  • Spare pins on the FPGA
  • 5v, 3.3v and GND

The UART is also used for the ESP Wi-fi module, and can't be used from the GPIO without removing the ESP module. I2C is also used to communicate with the real time clock module.

The GPIO is not populated and requires a socket to be installed (2 x 10 IDC 2.54mm spc. Male Pin Header). Pull up/down resistors may be required for some pins to limit current.

J15 position on circuit board
GPIO pinout image

In June 2019 it was announced that pins 4 and 17 of J15 would be used for two additional keyboard connections on full cased Nexts. Final specs have not yet been finalised.