XADC D1 Register: Difference between revisions
From SpecNext Wiki
updated to 78a6ee50 |
Correct incorrect register number to correct : Number=$FA as per https://gitlab.com/SpectrumNext/ZX_Spectrum_Next_FPGA/-/blob/master/cores/zxnext/nextreg.txt |
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| Line 1: | Line 1: | ||
{{NextRegister | {{NextRegister | ||
|Number=$ | |Number=$FA | ||
|Readable=Yes | |Readable=Yes | ||
|Writable=Yes | |Writable=Yes | ||
Revision as of 23:33, 6 April 2025
| Number | TBRegisterNumber::$FA |
|---|---|
| Readable | TBRegisterReadable::Yes |
| Writable | TBRegisterWritable::Yes |
| Short Description | ShortDesc::Issue 4 only |
bits 7:0 = MSB data connected to XADC DRP data bus D15:8
DRP reads store result here, DRP writes take value from here