Difference between revisions of "DMA interrupt enable 2"

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(updated to 78a6ee50)
 
(updated to 78a6ee50)
 
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soft reset = 0x00
 
soft reset = 0x00
 +
 +
Because interrupts are only sampled at the end of an instruction by the Z80, each time the dma is interrupted one instruction of progress is made in the main program.

Latest revision as of 12:37, 3 November 2024

Number $CE
Readable Yes
Writable Yes
Short Description UART Interrupts that can override DMA
 bit 7 = Reserved must be zero
 bit 6 = UART1 Tx empty
 bit 5 = UART1 Rx half full     \ shared
 bit 4 = UART1 Rx available     / interrupt
 bit 3 = Reserved must be zero
 bit 2 = UART0 Tx empty
 bit 1 = UART0 Rx half full     \ shared
 bit 0 = UART0 Rx available     / interrupt
  • Set bits indicate the corresponding interrupt will interrupt a dma operation when in hw im2 mode

soft reset = 0x00

Because interrupts are only sampled at the end of an instruction by the Z80, each time the dma is interrupted one instruction of progress is made in the main program.