Interrupt Status 2 Register

Number	TBRegisterNumber::$CA
Readable	TBRegisterReadable::Yes
Writable	TBRegisterWritable::Yes
Short Description	ShortDesc::Has UART interrupt happened?

bit 7 = Reserved must be zero
 bit 6 = UART1 Tx empty
 bit 5 = UART1 Rx half full    \ shared
 bit 4 = UART1 Rx available    / interrupt
 bit 3 = Reserved must be zero
 bit 2 = UART0 Tx empty
 bit 1 = UART0 Rx half full    \ shared
 bit 0 = UART0 Rx available    / interrupt

• (R) Set bits indicate the device generated an interrupt in the past or an interrupt is pending
• (W) Set bits clear the status. In hw im2 mode the status will continue to read as set until the interrupt pending condition is cleared