Interrupt Status 1 Register: Difference between revisions

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updated to 78a6ee50
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Revision as of 12:28, 3 November 2024

Number TBRegisterNumber::$C9
Readable TBRegisterReadable::Yes
Writable TBRegisterWritable::Yes
Short Description ShortDesc::has ctc interrupt occurred?
 bit 7 = ctc channel 7 zc/to
 bit 6 = ctc channel 6 zc/to
 bit 5 = ctc channel 5 zc/to
 bit 4 = ctc channel 4 zc/to
 bit 3 = ctc channel 3 zc/to
 bit 2 = ctc channel 2 zc/to
 bit 1 = ctc channel 1 zc/to
 bit 0 = ctc channel 0 zc/to
  • (R) Set bits indicate the device generated an interrupt in the past or an interrupt is pending
  • (W) Set bits clear the status. In hw im2 mode the status will continue to read as set until the interrupt pending condition is cleared