Difference between revisions of "Anti-brick Register"

Latest revision as of 11:19, 3 November 2024

Number	$10
Readable	Yes
Writable	Yes
Short Description	Used within the Anti-brick system.

Read bit mapped:

Bit	Effect
7	Reserved
6-2	Core ID
1	Button DRIVE (DivMMC) is pressed
0	Button M1 (Multiface) is pressed

Write bit mapped:

Bit	Effect
7	Start selected core (reboot FPGA)
6-5	Reserved, must be 0
4-0	Core ID 0-31 (default is 2) (only in config mode) *

 * A write of an out of range core id is ignored; this is the preferred way to determine max id

Note that in normal running pressing the DivMMC or Multiface button creates an NMI which halts any running program, and the reflashable core must be loaded before any user code is run. This means that unless you are rewriting the entire firmware from scratch this register is probably not useful.

@@ Line 9: / Line 9: @@
 ! Bit !! Effect
 |-
-| 7-2 || Reserved, 0
+| 7 || Reserved
 |-
-| 1 || DivMMC button pressed
+| 6-2 || Core ID
 |-
-| 0 || Multiface button pressed
+| 1 || Button DRIVE (DivMMC) is pressed
+|-
+| 0 || Button M1 (Multiface) is pressed
 |}
-'''Write''' bit mapped (only in config mode):
+'''Write''' bit mapped:
 {| class="wikitable"
 ! Bit !! Effect
 |-
-| 7 || If 1 start selected core, if 0 FPGA loads the fixed anti-brick core
+| 7 || Start selected core (reboot FPGA)
 |-
 | 6-5 || Reserved, must be 0
 |-
-| 4-0 || Core ID 0-31 (default is 2)
+| 4-0 || Core ID 0-31 (default is 2) (only in config mode) *
 |}
+  * A write of an out of range core id is ignored; this is the preferred way to determine max id
 Note that in normal running pressing the DivMMC or Multiface button creates an NMI which halts any running program, and the reflashable core must be loaded before any user code is run. This means that unless you are rewriting the entire firmware from scratch this register is probably not useful.