Difference between revisions of "GPIO Socket (J15)"
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* I2C serial protocol | * I2C serial protocol | ||
* UART | * UART | ||
| − | * Spare pins on the FPGA | + | * Spare pins on the [[FPGA]] |
* 5v, 3.3v and GND | * 5v, 3.3v and GND | ||
| − | The UART is also used for the ESP Wi-fi module, and can't be used from the GPIO without removing the ESP module. I2C is also used to communicate with the real time clock module. | + | The UART is also used for the [[ESP8266-01|ESP Wi-fi module]], and can't be used from the GPIO without removing the ESP module. I2C is also used to communicate with the [[RTC|real time clock]] module. |
| − | The GPIO is not populated and requires a socket to be installed (2 x 10 IDC 2.54mm spc. Male Pin Header). Pull up/down | + | The GPIO is not populated and requires a socket to be installed (2 x 10 IDC 2.54mm spc. Male Pin Header). Pull up/down resistors may be required for some pins to limit current. |
[[Image:NEXT GPIO location.jpg|thumb|J15 position on circuit board]] | [[Image:NEXT GPIO location.jpg|thumb|J15 position on circuit board]] | ||
[[Image:NEXT_GPIO.png|thumb|GPIO pinout image]] | [[Image:NEXT_GPIO.png|thumb|GPIO pinout image]] | ||
| − | In June 2019 it was announced that pins 4 and 17 of J15 would be used for two additional keyboard connections on full cased Nexts. | + | In June 2019 it was announced that pins 4 and 17 of J15 would be used for two additional keyboard connections on full cased Nexts. This is factory fitted on 2B boards with a two slot connector for the additional two lines on a third membrane tail. The extra data is handled by the VHDL in the FPGA so it still appears as a standard 48K Membrane but, without the complexity of three layers needed. |
| + | |||
| + | This change does mean it is slightly harder to use J15 as the socket overlaps some ajoining holes slightly. | ||
Latest revision as of 21:36, 4 March 2020
The GPIO socket, marked J15 on the circuit board, allows access to several different power and data lines:
- I2C serial protocol
- UART
- Spare pins on the FPGA
- 5v, 3.3v and GND
The UART is also used for the ESP Wi-fi module, and can't be used from the GPIO without removing the ESP module. I2C is also used to communicate with the real time clock module.
The GPIO is not populated and requires a socket to be installed (2 x 10 IDC 2.54mm spc. Male Pin Header). Pull up/down resistors may be required for some pins to limit current.
In June 2019 it was announced that pins 4 and 17 of J15 would be used for two additional keyboard connections on full cased Nexts. This is factory fitted on 2B boards with a two slot connector for the additional two lines on a third membrane tail. The extra data is handled by the VHDL in the FPGA so it still appears as a standard 48K Membrane but, without the complexity of three layers needed.
This change does mean it is slightly harder to use J15 as the socket overlaps some ajoining holes slightly.