Difference between revisions of "Internal Port Decoding b0-7 Register"

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m (core 3.0 changes/refresh)
(core 3.0 changes/refresh)
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All bits are set to 1 upon soft reset.
 
All bits are set to 1 upon soft reset.
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The internal port decoding enables always apply.
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When the expansion bus is on, the expansion port decoding (Next Registers $86-$89) enables are logically ANDed with the internal enables (Next Registers $82-$85). A zero bit indicates the internal device is disabled.
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If the expansion bus is on, this allows I/O cycles for disabled internal ports to propagate to the expansion bus, otherwise corresponding I/O cycles to the expansion bus are filtered.
  
 
(note: Next registers with number higher than $7F are inaccessible from Copper code)
 
(note: Next registers with number higher than $7F are inaccessible from Copper code)

Revision as of 09:14, 12 November 2019

Number $82
Readable Yes
Writable Yes
Short Description Enabling internal ports decoding
Bit Description
7 Enabling Kempston Joystick 2, Joystick I/O ($xx37 / 55) (also MD2 controller)
6 Enabling Kempston Joystick ($xx1F / 31) (also MD1 controller)
5 Enabling Datagear DMA Port ($xx6B / 107)
4 Enabling +3 floating bus
3 Enabling Plus 3 Memory Paging Control ($1FFD / 8189)
2 Enabling Next Memory Bank Select ($DFFD / 57341)
1 Enabling Memory Paging Control ($7FFD / 32765)
0 Enabling Timex Sinclair Video Mode Control ($xxFF / 255)

All bits are set to 1 upon soft reset.

The internal port decoding enables always apply.

When the expansion bus is on, the expansion port decoding (Next Registers $86-$89) enables are logically ANDed with the internal enables (Next Registers $82-$85). A zero bit indicates the internal device is disabled.

If the expansion bus is on, this allows I/O cycles for disabled internal ports to propagate to the expansion bus, otherwise corresponding I/O cycles to the expansion bus are filtered.

(note: Next registers with number higher than $7F are inaccessible from Copper code)