View source for Expansion Bus Decoding b8-15 Register

{{NextRegister
|Number=$87
|Readable=Yes
|Writable=Yes
|ShortDesc=When expansion bus is enabled: Internal ports decoding mask
}}
{|class="wikitable"
! Bit !! Description
|-
| 7 || (bit 15) Masking decoding: {{PortNo|$123B}}
|-
| 6 || (bit 14) Masking decoding: {{PortNo|$xx57}}, {{PortNo|$xx5B}} and {{PortNo|$303B}}
|-
| 5 || (bit 13) Masking decoding: {{PortNo|$FADF}}, {{PortNo|$FBDF}} and {{PortNo|$FFDF}}
|-
| 4 || (bit 12) Masking decoding: {{PortNo|$133B}}, {{PortNo|$143B}} and {{PortNo|$153B}} (UART)
|-
| 3 || (bit 11) Masking decoding: {{PortNo|$xxE7}} and {{PortNo|$xxEB}} (SPI)
|-
| 2 || (bit 10) Masking decoding: {{PortNo|$103B}} and {{PortNo|$113B}}
|-
| 1 || (bit 9) Masking decoding: Multiface (two variable ports)
|-
| 0 || (bit 8) Masking decoding: {{PortNo|$xxE3}} (DivMMC control)
|}

since core3.1.1: all bits are set to 1 when: soft reset and bit 31 is clear OR hard reset and bit 31 is set (otherwise content is kept intact). <del>All bits are set to 1 upon hard reset.</del>

When the expansion bus is on, the expansion port decoding mask (Next Registers $86-$89) is logically ANDed with the internal enables (Next Registers $82-$85). A zero bit indicates the internal device is disabled.

If the expansion bus is on, this allows I/O cycles for disabled internal ports to propagate to the expansion bus, otherwise corresponding I/O cycles to the expansion bus are filtered.

(note: Next registers with number higher than $7F are inaccessible from Copper code)