Difference between revisions of "Video Line Interrupt Control Register"

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(further details from Jim in forum post (timing of line interrupts))
m (7 revisions imported)
(No difference)

Revision as of 10:00, 14 April 2019

Number $22
Readable Yes
Writable Yes
Short Description Controls the timing of raster interrupts and the ULA frame interrupt.
Bit Function
7 (R) INT signal (even when Z80N has interrupts disabled) (1 = interrupt is requested)

(W) Reserved, must be 0

6-3 Reserved, must be 0
2 If 1 disables original ULA interrupt (Reset to 0 after a reset)
1 If 1 enables Line Interrupt (Reset to 0 after a reset)
0 MSB of Line Interrupt line value (Reset to 0 after a reset)

The line interrupt value uses coordinate system of Copper coprocessor, i.e. line 0 is the first line of pixels. But the line-interrupt happens already when the previous line's display area is finished (i.e. the raster-line counter still reads "previous line" and not the one programmed for interrupt) (the INT signal is raised when horizontal position is somewhere between 256-319 standard pixels and previous line drawing is finished). So the code in interrupt handler will start execution when the display beam is still in H-BLANK area and just preparing to start beaming the desired line.

The LSB part of desired interrupt line is in Video Line Interrupt Value Register ($23).