Difference between revisions of "Video Line Interrupt Control Register"

Latest revision as of 09:22, 27 April 2020

Number	$22
Readable	Yes
Writable	Yes
Short Description	Controls the timing of raster interrupts and the ULA frame interrupt.

Bit	Function
7	(R) INT signal (even when Z80N has interrupts disabled) (1 = interrupt is requested) (W) Reserved, must be 0
6-3	Reserved, must be 0
2	If 1 disables original ULA interrupt (Reset to 0 after a reset)
1	If 1 enables Line Interrupt (Reset to 0 after a reset)
0	MSB of Line Interrupt line value (Reset to 0 after a reset)

The line interrupt value uses coordinate system of Copper coprocessor, i.e. line 0 is the first line of pixels. But the line-interrupt happens already when the previous line's pixel area is finished (i.e. the raster-line counter still reads "previous line" and not the one programmed for interrupt). The INT signal is raised while display beam horizontal position is between 256-319 standard pixels, precise timing of interrupt handler execution then depends on how-quickly/if the Z80 will process the INT signal.

The LSB part of desired interrupt line is in Video Line Interrupt Value Register ($23).

Since core 3.1.5 the numbering of lines can be offset by Vertical Video Line Offset Register ($64).

@@ Line 20: / Line 20: @@
 |}
-The line interrupt value uses coordinate system of [https://gitlab.com/thesmog358/tbblue/blob/master/docs/extra-hw/copper/COPPER-v0.1c.TXT Copper coprocessor], i.e. line 0 is the first line of pixels. But the line-interrupt happens already when the previous line's display area is finished (i.e. the raster-line counter still reads "previous line" and not the one programmed for interrupt) (the INT signal is raised when horizontal position is somewhere between 256-319 standard pixels and previous line drawing is finished). So the code in interrupt handler will start execution when the display beam is still in H-BLANK area and just preparing to start beaming the desired line.
+The line interrupt value uses coordinate system of [https://gitlab.com/thesmog358/tbblue/blob/master/docs/extra-hw/copper/COPPER-v0.1c.TXT Copper coprocessor], i.e. line 0 is the first line of pixels. But the line-interrupt happens already when the previous line's pixel area is finished (i.e. the raster-line counter still reads "previous line" and not the one programmed for interrupt). The INT signal is raised while display beam horizontal position is between 256-319 standard pixels, precise timing of interrupt handler execution then depends on how-quickly/if the Z80 will process the INT signal.
 The LSB part of desired interrupt line is in {{NextRegNo|$23}}.
+Since core 3.1.5 the numbering of lines can be offset by {{NextRegNo|$64}}.