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 NumberReadableWritableDescription
Palette Value Register$41truetrueUse to set/read 8-bit colours of the ULANext palette.
Enhanced ULA Ink Color Mask$42truetrueSpecifies mask to extract ink colour from attribute cell value in ULANext mode.
Enhanced ULA Control Register$43truetrueEnables or disables Enhanced ULA interpretation of attribute values and toggles active palette.
Enhanced ULA Palette Extension$44truetrueUse to set 9-bit (2-byte) colours of the Enhanced ULA palette, or to read second byte of colour.
Transparency colour fallback Register$4Atruetrue8-bit colour to be used when all layers contain transparent pixel.
Sprites Transparency Index Register$4BtruetrueIndex into sprite palette (of "transparent" colour).
Tilemap Transparency Index Register$4CtruetrueIndex into Tilemap palette (of "transparent" colour).
Memory management slot 0 bank$50truetrueSelects the 8k-bank stored in 8k-slot 0 (see Memory map).
Memory management slot 1 bank$51truetrueSelects the 8k-bank stored in 8k-slot 1 (see Memory map).
Memory management slot 2 bank$52truetrueSelects the 8k-bank stored in 8k-slot 2 (see Memory map).
Memory management slot 3 bank$53truetrueSelects the 8k-bank stored in 8k-slot 3 (see Memory map).
Memory management slot 4 bank$54truetrueSelects the 8k-bank stored in 8k-slot 4 (see Memory map).
Memory management slot 5 bank$55truetrueSelects the 8k-bank stored in 8k-slot 5 (see Memory map).
Memory management slot 6 bank$56truetrueSelects the 8k-bank stored in 8k-slot 6 (see Memory map).
Memory management slot 7 bank$57truetrueSelects the 8k-bank stored in 8k-slot 7 (see Memory map).
Copper Data$60falsetrueUsed to upload code to the Copper.
Copper Control Low Byte$61truetrueHolds low byte of Copper control bits.
Copper Control High Byte$62truetrueHolds high byte of Copper control flags.
Copper Data 16-bit Write Register$63falsetrueUsed to upload code to the Copper.
Vertical Video Line Offset Register$64truetrueOffset numbering of raster lines in copper/interrupt/active register
ULA Control Register$68truetrueDisable ULA, controls ULA mixing/blending, enable ULA+
Display Control 1 Register$69truetrueLayer2, ULA shadow, Timex $FF port
LoRes Control Register$6AtruetrueLoRes Radastan mode
Tilemap Control Register$6BtruetrueControls Tilemap mode.
Default Tilemap Attribute Register$6CtruetrueDefault tile attribute for 8-bit only maps.
Tilemap Base Address Register$6EtruetrueBase address of the 40x32 or 80x32 tile map (similar to text-mode of other computers).
Tile Definitions Base Address Register$6FtruetrueBase address of the tiles' graphics.
Layer 2 Control Register$70truetrueLayer 2 resolution, palette offset
Layer 2 X Offset MSB Register$71truetrueSets the pixel offset used for drawing Layer 2 graphics on the screen.
Sprite port-mirror Attribute 0 (with INC) Register$75falsetrueSame as Sprite port-mirror Attribute 0 Register ($35) (write first byte of sprite-attributes), plus increments Sprite port-mirror Index Register ($34)
Sprite port-mirror Attribute 1 (with INC) Register$76falsetrueSame as Sprite port-mirror Attribute 1 Register ($36) (write second byte of sprite-attributes), plus increments Sprite port-mirror Index Register ($34)
Sprite port-mirror Attribute 2 (with INC) Register$77falsetrueSame as Sprite port-mirror Attribute 2 Register ($37) (write third byte of sprite-attributes), plus increments Sprite port-mirror Index Register ($34)
Sprite port-mirror Attribute 3 (with INC) Register$78falsetrueSame as Sprite port-mirror Attribute 3 Register ($38) (write fourth byte of sprite-attributes), plus increments Sprite port-mirror Index Register ($34)
Sprite port-mirror Attribute 4 (with INC) Register$79falsetrueThe same as Sprite port-mirror Attribute 4 Register ($39) (write fifth byte of sprite-attributes), plus increments Sprite port-mirror Index Register ($34)
User Storage 0 Register$7Ftruetrue8-bit storage for user
Expansion Bus Enable Register$80truetrueExpansion bus enable/config
Expansion Bus Control Register$81truetrueExpansion bus controls
Internal Port Decoding b0-7 Register$82truetrueEnabling internal ports decoding
Internal Port Decoding b8-15 Register$83truetrueEnabling internal ports decoding
Internal Port Decoding b16-23 Register$84truetrueEnabling internal ports decoding
Internal Port Decoding b24-31 Register$85truetrueEnabling internal ports decoding
Expansion Bus Decoding b0-7 Register$86truetrueWhen expansion bus is enabled: Internal ports decoding mask
Expansion Bus Decoding b8-15 Register$87truetrueWhen expansion bus is enabled: Internal ports decoding mask
Expansion Bus Decoding b16-23 Register$88truetrueWhen expansion bus is enabled: Internal ports decoding mask
Expansion Bus Decoding b24-31 Register$89truetrueWhen expansion bus is enabled: Internal ports decoding mask
Expansion Bus I/O Propagate Register$8AtruetrueMonitoring internal I/O or adding external keyboard
Alternate ROM$8CtruetrueEnable alternate ROM or lock 48k ROM
Memory Mapping Register$8EtruetrueControl classic Spectrum memory mapping
Pi GPIO Output Enable Register$90-$93truetrueEnables GPIO pins output
Pi GPIO Register$98-$9BtruetrueGPIO pins mapped to Next Register
Pi Peripheral Enable Register$A0truetrueEnable Pi peripherals: UART, Pi hats, I2C, SPI
Pi I2S Audio Control Register$A2truetruePi I2S controls
Pi I2S Clock Divide Register$A3truetruePi I2S clock divide in master mode.
ESP WiFi GPIO Output Register$A8truetrueESP WiFi GPIO Output
ESP WiFi GPIO Register$A9truetrueESP WiFi GPIO Read/Write
Extended Keys 0 Register$B0truefalseRead Next keyboard compound keys separately
Extended Keys 1 Register$B1truefalseRead Next keyboard compound keys separately
DivMMC Trap Enable 1 Register$B2truetrueDivMMC trap configuration
DivMMC Trap Enable 2 Register$B4truetrueDivMMC trap configuration
Debug LED Control Register$FFfalsetrueTurns debug LEDs on and off on TBBlue implementations that have them.