Property: ShortDesc
From SpecNext official Wiki
This is a property of type Text.
- Description
- Short text description. (en)
T
8-bit colour to be used when all layers contain transparent pixel. +
U
8-bit storage for user +
D
<del>DivMMC trap configuration</del> +
<del>DivMMC trap configuration</del> +
P
<del>Pi I2S clock divide in master mode.</del> +
ABC/ACB [[Stereo]], Internal Speaker, [[SpecDrum]], [[Enhanced ULA|Timex Video Modes]], [[Turbo Sound Next]], RAM contention and [un]lock 128k paging. +
T
Base address of the 40x32 or 80x32 tile map (similar to text-mode of other computers). +
Base address of the tiles' graphics. +
C
CTC 8 channels 0x183b - 0x1f3b +
P
Chooses an palette element (index) to manipulate with +
U
Configuration of UART interfaces +
M
Control classic Spectrum memory mapping +
C
Controls (resets) the clip-window registers indices. +
P
Controls ROM paging and special paging options from the +2a/+3. +
T
Controls Timex Sinclair video modes and colours in hi-res mode. +
M
Controls Z8410 DMA chip via MB02 standard. +
T
Controls [[Tilemap]] mode. +
U
Controls border color and base Spectrum audio settings. +
T
Controls stereo channels and selects active sound chip and sound chip channel. +
V
Controls the timing of raster interrupts and the ULA frame interrupt. +
D
Controls zxnDMA chip +
DAC B mirror, read current I2S left MSB +
DAC C mirror, read current I2S right MSB +
Default tile attribute for 8-bit only maps. +
U
Disable ULA, controls ULA mixing/blending, enable ULA+ +
D
E
ESP WiFi GPIO Output +
ESP WiFi GPIO Read/Write +
P
Enable Pi peripherals: UART, Pi hats, I2C, SPI +
A
Enable alternate ROM or lock 48k ROM +
P
Enables GPIO pins output +
Enables [[CPU Speed control|CPU Speed key]], [[DivMMC]], [[Multiface]], [[Mouse]] and [[AY|AY audio]]. +
L
Enables [[Layer 2]] and controls paging of layer 2 screen into lower memory. +
E
Enables or disables Enhanced ULA interpretation of attribute values and toggles active palette. +
S
Enables/disables [[Sprites]] and [[Video_Modes#LoRes_Layer.2FRadasjimian_Mode|Lores Layer]], and chooses priority of sprites and [[Layer 2]]. +
I
Enabling internal ports decoding +
Enabling internal ports decoding +
Enabling internal ports decoding +
Enabling internal ports decoding +
E
Expansion bus controls +
Expansion bus enable/config +
P
GPIO pins mapped to Next Register +
K
High data to PS/2 Keymap (MSB of data in bit 0) +
C
Holds high byte of [[Copper]] control flags. +
Holds low byte of [[Copper]] control bits. +
A
Holds the MSB (only, as bit 0) of the raster line currently being drawn. +
V
Holds the eight LSBs of the line on which a raster interrupt should occur. +
A
Holds the eight LSBs of the raster line currently being drawn. +
M
Identifies [[TBBlue]] board type. Should always be 10 on Next. +
C
Identifies core (FPGA image) version (sub minor number). +
Identifies core (FPGA image) version. +
M
Identifies timing and machine type. +
N
Identifies type of last reset. Can be written to force reset. +
C
In config mode, allows RAM to be mapped to ROM area. +
T
Index into Tilemap palette (of "transparent" colour). +
S
Index into sprite palette (of "transparent" colour). +
K
Kempston interface second joystick variant and controls joystick I/O. +
L
Layer 2 resolution, palette offset +
D
Layer2, ULA shadow, Timex $FF port +
L
LoRes Radastan mode +
K
Low eight LSBs of PS/2 Keymap data. +
E
Monitoring internal I/O or adding external keyboard +
P
Mouse buttons and DPI config +
S
Nextreg port-mirror to write directly into "byte 5" of [[:Sprite Attribute Upload|Sprite Attribute Upload]] ($xx57 / 87). +
Nextreg port-mirror to write directly into "byte 2" of [[:Sprite Attribute Upload|Sprite Attribute Upload]] ($xx57 / 87). +
Nextreg port-mirror to write directly into "byte 1" of [[:Sprite Attribute Upload|Sprite Attribute Upload]] ($xx57 / 87). +
Nextreg port-mirror to write directly into "byte 3" of [[:Sprite Attribute Upload|Sprite Attribute Upload]] ($xx57 / 87). +
Nextreg port-mirror to write directly into "byte 4" of [[:Sprite Attribute Upload|Sprite Attribute Upload]] ($xx57 / 87). +
V
Offset numbering of raster lines in copper/interrupt/active register +
S
Output to SpecDrum DAC. +
K
PS/2 Keymap address LSB. +
PS/2 Keymap address MSB, read (pending) first byte of palette colour +
P
Pi I2S controls +
L
Pixel X offset (0..255) to use when drawing LoRes Layer. +
U
Pixel X offset (0..255) to use when drawing ULA Layer. +
L
Pixel Y offset (0..191) to use when drawing LoRes Layer. +
U
Pixel Y offset (0..191) to use when drawing ULA Layer. +
N
Provides additional bank select bits for extended memory. +
E
Read Next keyboard compound keys separately +
Read Next keyboard compound keys separately +
T
Reads and/or writes the selected TBBlue control register. +
K
Reads buttons on Kempston Mouse. +
U
K
Reads movement of joysticks using Kempston interface. +
S
Same as [[:Sprite port-mirror Attribute 0 Register|Sprite port-mirror Attribute 0 Register]] ($35) (write first byte of sprite-attributes), plus increments [[:Sprite port-mirror Index Register|Sprite port-mirror Index Register]] ($34) +
Same as [[:Sprite port-mirror Attribute 3 Register|Sprite port-mirror Attribute 3 Register]] ($38) (write fourth byte of sprite-attributes), plus increments [[:Sprite port-mirror Index Register|Sprite port-mirror Index Register]] ($34) +
Same as [[:Sprite port-mirror Attribute 1 Register|Sprite port-mirror Attribute 1 Register]] ($36) (write second byte of sprite-attributes), plus increments [[:Sprite port-mirror Index Register|Sprite port-mirror Index Register]] ($34) +
Same as [[:Sprite port-mirror Attribute 2 Register|Sprite port-mirror Attribute 2 Register]] ($37) (write third byte of sprite-attributes), plus increments [[:Sprite port-mirror Index Register|Sprite port-mirror Index Register]] ($34) +
M
Selects active RAM, ROM, and displayed screen. +
T
Selects active port for TBBlue/Next feature configuration. +
S
Selects sprite index 0..127 to be affected by writes to other Sprite ports (and mirrors). +
M
Selects the 8k-bank stored in 8k-slot 0 (see [[Memory map]]). +
Selects the 8k-bank stored in 8k-slot 1 (see [[Memory map]]). +
Selects the 8k-bank stored in 8k-slot 2 (see [[Memory map]]). +
Selects the 8k-bank stored in 8k-slot 3 (see [[Memory map]]). +
Selects the 8k-bank stored in 8k-slot 4 (see [[Memory map]]). +
Selects the 8k-bank stored in 8k-slot 5 (see [[Memory map]]). +
Selects the 8k-bank stored in 8k-slot 6 (see [[Memory map]]). +
Selects the 8k-bank stored in 8k-slot 7 (see [[Memory map]]). +
U