Difference between revisions of "Pi I2S Clock Divide Register"

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(core 3.1.5 changes/refresh)
 
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|Readable=Yes
 
|Readable=Yes
 
|Writable=Yes
 
|Writable=Yes
|ShortDesc=Pi I2S clock divide in master mode.
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|ShortDesc=<del>Pi I2S clock divide in master mode.</del>
 
}}
 
}}
bits 7:0 = Clock divide sets sample rate when in master mode (soft reset = decimal 11)
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The I2S master-mode was '''REMOVED''' in core3.1.5 as well as this register.
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<del>bits 7:0 = Clock divide sets sample rate when in master mode (soft reset = decimal 11)</del>
  
 
clock divider = 538461 / SampleRateHz - 1
 
clock divider = 538461 / SampleRateHz - 1

Latest revision as of 08:29, 27 April 2020

Number $A3
Readable Yes
Writable Yes
Short Description Pi I2S clock divide in master mode.

The I2S master-mode was REMOVED in core3.1.5 as well as this register.


bits 7:0 = Clock divide sets sample rate when in master mode (soft reset = decimal 11)

clock divider = 538461 / SampleRateHz - 1

i.e. SampleRateHz = 538461 / (clock divider + 1)

The default value corresponds to ~44871Hz sample rate.