Difference between revisions of "Peripheral 2 Register"

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(core 3.1.3 changes/refresh)
m (turbo becomes CPU Speed)
 
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|Readable=Yes
 
|Readable=Yes
 
|Writable=Yes
 
|Writable=Yes
|ShortDesc=Enables [[Acceleration|Acceleration key]], [[DivMMC]], [[Multiface]], [[Mouse]] and [[AY|AY audio]].
+
|ShortDesc=Enables [[CPU Speed control|CPU Speed key]], [[DivMMC]], [[Multiface]], [[Mouse]] and [[AY|AY audio]].
 
}}
 
}}
 
{| class="wikitable"
 
{| class="wikitable"
 
! Bit !! Function
 
! Bit !! Function
 
|-
 
|-
| 7 || Enable turbo mode key "F8", 0 = disabled (1 after Soft-reset)
+
| 7 || Enable CPU speed mode key "F8", 0 = disabled (1 after Soft-reset)
 
|-
 
|-
 
| 6 || core3.1.2: Divert BEEP-only to internal speaker (hard reset = 0)
 
| 6 || core3.1.2: Divert BEEP-only to internal speaker (hard reset = 0)
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|}
 
|}
  
The bit 7 doesn't prevent SW from setting up turbo mode by writing into {{NextRegNo|$07}}, it is used only to enable/disable the "F8" key toggle, similarly bit 5 enables "F3" key.
+
The bit 7 doesn't prevent SW from setting up different CPU speed by writing into {{NextRegNo|$07}}, it is used only to enable/disable the "F8" key toggle, similarly bit 5 enables "F3" key.
  
 
'''NEW in core 3.0:'''
 
'''NEW in core 3.0:'''

Latest revision as of 19:41, 20 September 2020

Number $06
Readable Yes
Writable Yes
Short Description Enables CPU Speed key, DivMMC, Multiface, Mouse and AY audio.
Bit Function
7 Enable CPU speed mode key "F8", 0 = disabled (1 after Soft-reset)
6 core3.1.2: Divert BEEP-only to internal speaker (hard reset = 0)

DMA mode (0 = zxnDMA, 1 = Z80 DMA) (0 after Hard-reset)

5 Enable "F3" key (50/60 Hz switch) (1 after Soft-reset) (was "Enable Lightpen" in core 2.0)
4 Enable DivMMC automap and DivMMC NMI by DRIVE button (0 after Hard-reset)
3 Enable multiface NMI by M1 button (hard reset = 0)
2 PS/2 mode (primary device: 0 = keyboard, 1 = mouse), exchanges the keyboard/mouse pins on the PS/2 connector (writeable only in config mode)
1-0 Audio chip mode (%00 = YM, %01 = AY, %1x = Disabled)

(core 3.0) %11 hold all AY in reset

The bit 7 doesn't prevent SW from setting up different CPU speed by writing into CPU Speed Register ($07), it is used only to enable/disable the "F8" key toggle, similarly bit 5 enables "F3" key.

NEW in core 3.0:

 bit 5 = enable F3 (50/60 Hz)
 bit 2 ps2mode only modifiable in config mode
 chip mode = 11 resets all AY

NEW in core 3.1.2:

 bit 6 = BEEP-only into internal speaker (DMA does use two I/O ports now)