Difference between revisions of "Next Reset Register"

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(core 3.0 changes)
 
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|ShortDesc=Identifies type of last reset. Can be written to force reset.
 
|ShortDesc=Identifies type of last reset. Can be written to force reset.
 
}}
 
}}
{| class="wikitable"
+
Read:
! Bit
+
  bit 7 = Indicates the reset signal to the expansion bus and esp is asserted
! Function
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  bits 6:2 = Reserved
|-
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  bit 1 = Indicates the last reset was a hard reset
| 7 || Reserved (write 0)
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  bit 0 = Indicates the last reset was a soft reset
|-
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  * Only one of bits 1:0 will be set
| 6 || Reserved
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Write:
|-
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  bit 7 = Assert and hold reset to the expansion bus and the esp wifi (hard reset = 0)
| 5 || Reserved
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  bits 6:2 = Reserved, must be 0
|-
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  bit 1 = Generate a hard reset (reboot)
| 4 || Reserved
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  bit 0 = Generate a soft reset
|-
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  * Hard reset has precedence
| 3 || Reserved
 
|-
 
| 2 || Read-only, indicates power-on reset
 
|-
 
| 1 || Indicates hard reset. Writing 1 causes a hard reset.
 
|-
 
| 0 || Indicates soft reset. Writing 1 causes a soft reset.
 
|}
 

Latest revision as of 11:32, 11 November 2019

Number $02
Readable Yes
Writable Yes
Short Description Identifies type of last reset. Can be written to force reset.

Read:

 bit 7 = Indicates the reset signal to the expansion bus and esp is asserted
 bits 6:2 = Reserved
 bit 1 = Indicates the last reset was a hard reset
 bit 0 = Indicates the last reset was a soft reset
 * Only one of bits 1:0 will be set

Write:

 bit 7 = Assert and hold reset to the expansion bus and the esp wifi (hard reset = 0)
 bits 6:2 = Reserved, must be 0
 bit 1 = Generate a hard reset (reboot)
 bit 0 = Generate a soft reset
 * Hard reset has precedence