Difference between revisions of "Machine Type Register"
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! Function | ! Function | ||
|- | |- | ||
| − | | 7 || (W) Lock Timing | + | | 7 || (W) Lock Timing (change timing in any mode) |
|- | |- | ||
| 7 || (R) Next write to {{NextRegNo|$44}} will affect colour byte: 0 = RRRGGGBB, 1 = p000000B | | 7 || (R) Next write to {{NextRegNo|$44}} will affect colour byte: 0 = RRRGGGBB, 1 = p000000B | ||
Revision as of 02:41, 3 February 2019
| Number | $03 |
|---|---|
| Readable | Yes |
| Writable | Yes |
| Short Description | Identifies timing and machine type. |
Only valid in IPL or config mode (0x0000-0x3FFF are mapped to the RAM instead of the internal ROM).
A write to this register disables the IPL.
A write with bit 7 set will be accepted in any mode to change only timing (bits 6-4).
| Bit | Function |
|---|---|
| 7 | (W) Lock Timing (change timing in any mode) |
| 7 | (R) Next write to Enhanced ULA Palette Extension ($44) will affect colour byte: 0 = RRRGGGBB, 1 = p000000B |
| 6-4 | Timing. %000-001: ZX 48k; %010: ZX 128k/+2 (Grey); %011: ZX +2A-B/+3e/Next Native; %100: Pentagon. |
| 3 | Reserved, must be 0 |
| 2-0 | Machine type. %000: Config mode; %001: ZX 48k; %010: ZX 128k/+2 (Grey); %011: ZX +2A-B/+3e/Next Native; %100: Pentagon. |