Difference between revisions of "Machine Type Register"
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| 6-4 || Display timing. %000-001: ZX 48k; %010: ZX 128k/+2 (Grey); %011: ZX +2A-B/+3e/Next Native; %100: Pentagon. | | 6-4 || Display timing. %000-001: ZX 48k; %010: ZX 128k/+2 (Grey); %011: ZX +2A-B/+3e/Next Native; %100: Pentagon. | ||
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− | | 3 || | + | | 3 || 1 to apply user lock on display timing (hard reset = 0) (since core 3.0.5) |
|- | |- | ||
| 2-0 || Machine type: | | 2-0 || Machine type: |
Revision as of 00:26, 5 December 2019
Number | $03 |
---|---|
Readable | Yes |
Writable | Yes |
Short Description | Identifies timing and machine type. |
A write to this register disables the bootrom in config mode
A write with bit 7 set will be accepted in any mode to change only display timing (bits 6-4).
Bit | Function |
---|---|
7 | (W) 1 to allow changes to bits 6:4 |
7 | (R) Next write to Enhanced ULA Palette Extension ($44) will affect colour byte: 0 = RRRGGGBB, 1 = p000000B |
6-4 | Display timing. %000-001: ZX 48k; %010: ZX 128k/+2 (Grey); %011: ZX +2A-B/+3e/Next Native; %100: Pentagon. |
3 | 1 to apply user lock on display timing (hard reset = 0) (since core 3.0.5) |
2-0 | Machine type:
%000: Config mode; %001: ZX 48k; %010: ZX 128k/+2 (Grey); %011: ZX +2A-B/+3e/Next Native; %100: Pentagon. Writeable only in config mode, may affect port decoding and enabling of some hardware. |