Difference between revisions of "Internal Port Decoding b24-31 Register"

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(core 3.0 changes/refresh)
 
(core 3.0 changes/refresh)
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All bits are set to 1 upon soft reset.
 
All bits are set to 1 upon soft reset.
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The internal port decoding enables always apply.
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When the expansion bus is on, the expansion port decoding (Next Registers $86-$89) enables are logically ANDed with the internal enables (Next Registers $82-$85). A zero bit indicates the internal device is disabled.
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If the expansion bus is on, this allows I/O cycles for disabled internal ports to propagate to the expansion bus, otherwise corresponding I/O cycles to the expansion bus are filtered.
  
 
(note: Next registers with number higher than $7F are inaccessible from Copper code)
 
(note: Next registers with number higher than $7F are inaccessible from Copper code)

Revision as of 10:16, 12 November 2019

Number $85
Readable Yes
Writable Yes
Short Description Enabling internal ports decoding
Bit Description
7-1 (bit 31-25) Reserved, use 1 (? to be confirmed)
0 (bit 24) Enabling ($BF3B) and ($FF3B) (ULA+)

All bits are set to 1 upon soft reset.

The internal port decoding enables always apply.

When the expansion bus is on, the expansion port decoding (Next Registers $86-$89) enables are logically ANDed with the internal enables (Next Registers $82-$85). A zero bit indicates the internal device is disabled.

If the expansion bus is on, this allows I/O cycles for disabled internal ports to propagate to the expansion bus, otherwise corresponding I/O cycles to the expansion bus are filtered.

(note: Next registers with number higher than $7F are inaccessible from Copper code)