Difference between revisions of "Expansion Bus Enable Register"

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(core 3.0.5 changes/refresh)
(core 3.1.3 changes/refresh)
 
Line 11: Line 11:
 
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| 7 || 1 to enable Expansion Bus
 
| 7 || 1 to enable Expansion Bus
 +
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 +
| 6 || (since core 3.1.3) 1 to enable romcs rom replacement from divmmc banks 14/15
 
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|-
 
| 5 || 1 to disable I/O cycles and ignore IORQULA
 
| 5 || 1 to disable I/O cycles and ignore IORQULA
Line 19: Line 21:
 
|-
 
|-
 
| 3 || 1 to enable Expansion Bus
 
| 3 || 1 to enable Expansion Bus
 +
|-
 +
| 2 || (since core 3.1.3) 1 to enable romcs rom replacement from divmmc banks 14/15
 
|-
 
|-
 
| 1 || 1 to disable I/O cycles and ignore IORQULA
 
| 1 || 1 to disable I/O cycles and ignore IORQULA

Latest revision as of 09:19, 30 March 2020

Number $80
Readable Yes
Writable Yes
Short Description Expansion bus enable/config
Bit Description
Values affecting machine immediately
7 1 to enable Expansion Bus
6 (since core 3.1.3) 1 to enable romcs rom replacement from divmmc banks 14/15
5 1 to disable I/O cycles and ignore IORQULA
4 1 to disable memory cycles and ignore ROMCS
After soft reset (will be copied to bits 7-4)
3 1 to enable Expansion Bus
2 (since core 3.1.3) 1 to enable romcs rom replacement from divmmc banks 14/15
1 1 to disable I/O cycles and ignore IORQULA
0 1 to disable memory cycles and ignore ROMCS

Set to 0 upon hard reset.

(new register since core 3.0.5)

(note: Next registers with number higher than $7F are inaccessible from Copper code)