Difference between revisions of "DivMMC Trap Enable 2 Register"

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(core 3.1.0 changes/refresh)
 
(core 3.1.3 changes/refresh)
 
Line 3: Line 3:
 
|Readable=Yes
 
|Readable=Yes
 
|Writable=Yes
 
|Writable=Yes
|ShortDesc=DivMMC trap configuration
+
|ShortDesc=<del>DivMMC trap configuration</del>
 
}}
 
}}
 +
 +
core3.1.3 status: '''NOT IMPLEMENTED YET'''
 +
 +
-----------------------
 +
 +
Possible implementation specs:
 +
 
(hard reset = 0x1B)
 
(hard reset = 0x1B)
 
     bits 7:5 = Reserved, must be 0
 
     bits 7:5 = Reserved, must be 0
Line 12: Line 19:
 
     bit 1 = (trap, delayed) enable 0x04C6, 0x0562
 
     bit 1 = (trap, delayed) enable 0x04C6, 0x0562
 
     bit 0 = (trap, delayed) enable 0x0066
 
     bit 0 = (trap, delayed) enable 0x0066
(new register since core3.1.0)
 

Latest revision as of 09:41, 30 March 2020

Number $B4
Readable Yes
Writable Yes
Short Description DivMMC trap configuration


core3.1.3 status: NOT IMPLEMENTED YET


Possible implementation specs:

(hard reset = 0x1B)

   bits 7:5 = Reserved, must be 0
   bit 4 = (trap, instant) enable 0x3D00 - 0x3DFF
   bit 3 = (trap, delayed) disable 0x1FF8 - 0x1FFF
   bit 2 = (trap, instant) enable 0x04CB, 0x056B
   bit 1 = (trap, delayed) enable 0x04C6, 0x0562
   bit 0 = (trap, delayed) enable 0x0066