Difference between revisions of "DivMMC Trap Enable 1 Register"

Latest revision as of 10:40, 30 March 2020

Number	$B2
Readable	Yes
Writable	Yes
Short Description	~~DivMMC trap configuration~~

core3.1.3 status: NOT IMPLEMENTED YET

Possible implementation specs:

(hard reset = 0x83)

   bit 7 = (trap, delayed) enable 0x0038
   bit 6 = (trap, delayed) enable 0x0030
   bit 5 = (trap, delayed) enable 0x0028
   bit 4 = (trap, delayed) enable 0x0020
   bit 3 = (trap, delayed) enable 0x0018
   bit 2 = (trap, delayed) enable 0x0010
   bit 1 = (trap, delayed) enable 0x0008
   bit 0 = (trap, delayed) enable 0x0000

@@ Line 3: / Line 3: @@
 |Readable=Yes
 |Writable=Yes
-|ShortDesc=DivMMC trap configuration
+|ShortDesc=<del>DivMMC trap configuration</del>
 }}
+core3.1.3 status: '''NOT IMPLEMENTED YET'''
+-----------------------
+Possible implementation specs:
 (hard reset = 0x83)
      bit 7 = (trap, delayed) enable 0x0038
@@ Line 14: / Line 21: @@
      bit 1 = (trap, delayed) enable 0x0008
      bit 0 = (trap, delayed) enable 0x0000
-(new register since core3.1.0)